mcspi.h File Reference

Introduction

This file contains the function prototypes for the device abstraction layer for MCSPI. It also contains necessary structure, enum and macro definitions.

Programming sequence of MCSPI is as follows:

1. MCSPI can be put into reset by calling the API McSPIReset.
2. MCSPI CS can be enabled by calling the API McSPICSEnable.
3. Polarity of CS can be configured by calling the API McSPICSPolarityConfig.
4. Master Mode configurations by calling the API McSPIMasterModeConfig.
5. MCSPI output clock can be configured by calling the API McSPIClkConfig.
6. Word length of MCSPI can be configured by calling the API McSPIWordLengthSet.
7. Transmit Fifo can be enabled/disabled by calling the API McSPITxFIFOConfig.
8. Receive Fifo can be enabled/disabled by calling the API McSPIRxFIFOConfig.
9. Assert the CS of MCSPI by calling the API McSPICSAssert.
10. Deassert the CS of MCSPI by calling the API McSPICSDeAssert.
11. MCSPI interrupts can be enabled by calling the API McSPIIntEnable and disabled by calling the API McSPIIntDisable.
12. MCSPI channel can be enabled by calling the API McSPIChannelEnable and disabled by calling the API McSPIChannelDisable.
13. Status on MCSPI interrupts can be checked by calling the API McSPIIntStatusGet.
14. MCSPI interrupts status can be cleared by calling the API McSPIIntStatusClear.
15. Data to be transmitted is to be written to the transmit register by calling the API McSPITransmitData.
16. Received data into the MCSPI receive register can be read by calling the API McSPIReceiveData.

Go to the source code of this file.

Macros
#define	MCSPI_CHANNEL_0   (0U)
	McSPI channel 0 is used for data communication. More...
#define	MCSPI_CHANNEL_1   (1U)
	McSPI channel 1 is used for data communication. More...
#define	MCSPI_CHANNEL_2   (2U)
	McSPI channel 2 is used for data communication. More...
#define	MCSPI_CHANNEL_3   (3U)
	McSPI channel 3 is used for data communication. More...
#define	MCSPI_CLK_MODE_0
	McSPI clock Mode 0 is selected SPICLK is active high and sampling occurs on the rising edge. More...
#define	MCSPI_CLK_MODE_1
	McSPI clock Mode 1 is selected SPICLK is active high and sampling occurs on the falling edge. More...
#define	MCSPI_CLK_MODE_2
	McSPI clock Mode 2 is selected SPICLK is active low and sampling occurs on the falling edge. More...
#define	MCSPI_CLK_MODE_3
	McSPI clock Mode 3 is selected SPICLK is active low and sampling occurs on the rising edge. More...
#define	MCSPI_REG_OFFSET   (0x14U)
	McSPI Register Offset for MCSPI_CHxCONF, MCSPI_CHxSTAT, MCSPI_CHxCTRL, MCSPI_TXx and MCSPI_RXx register sets. More...
#define	MCSPI_CHCONF(x)
	Base address of McSPI Channel configuration : MCSPI_CHCONF(x) More...
#define	MCSPI_CHSTAT(x)
	Base address of McSPI Channel status : McSPI_CHSTAT(x) More...
#define	MCSPI_CHCTRL(x)
	Base address of McSPI_CHCTRL(x) which is used to enable channel. More...
#define	MCSPI_CHTX(x)
	Base address of McSPI_CHTX(x) which is used to store data to be transmitted. More...
#define	MCSPI_CHRX(x)
	Base address of McSPI_CHRX(x) which is used to store data to be received. More...
#define	MCSPI_WORD_LENGTH_MIN   ((uint32_t) 4U)
	Minumum word lengths that is valid for McSPI channel configuration. More...
#define	MCSPI_WORD_LENGTH_MAX   ((uint32_t) 32U)
	Maximum word lengths that is valid for McSPI channel configuration. More...
#define	MCSPI_WORD_LENGTH(n)
	Values used to set the word length for McSPI communication 'n' can take values only between 4 <= n <= 32. More...
#define	MCSPI_CS_TCS_0PNT5_CLK
	chip select time control(TCS) configuration : Zero interface clock cycle between CS toggling and first or last edge of SPI clock More...
#define	MCSPI_CS_TCS_1PNT5_CLK
	chip select time control(TCS) configuration : One interface clock cycle between CS toggling and first or last edge of SPI clock More...
#define	MCSPI_CS_TCS_2PNT5_CLK
	chip select time control(TCS) configuration : Two interface clock cycles between CS toggling and first or last edge of SPI clock More...
#define	MCSPI_CS_TCS_3PNT5_CLK
	chip select time control(TCS) configuration : Three interface clock cycles between CS toggling and first or last edge of SPI clock More...
#define	MCSPI_START_BIT_POL_LOW   (MCSPI_CH0CONF_SBPOL_LOWLEVEL)
	Low polarity is set for start bit for McSPI communication. More...
#define	MCSPI_START_BIT_POL_HIGH   (MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
	High polarity is set for start bit for McSPI communication. More...
#define	MCSPI_TX_RX_MODE
	Transmit-receive mode of McSPI peripheral in master mode is configured. More...
#define	MCSPI_RX_ONLY_MODE
	Only Receive mode of McSPI peripheral in master mode is configured. More...
#define	MCSPI_TX_ONLY_MODE
	Only Transmit mode of McSPI peripheral in master mode is configured. More...
#define	MCSPI_DATA_LINE_COMM_MODE_0
	Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission Data Line 0 (SPIDAT[0]) selected for transmission. More...
#define	MCSPI_DATA_LINE_COMM_MODE_1
	Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission No transmission on Data Line 0 (SPIDAT[0]) More...
#define	MCSPI_DATA_LINE_COMM_MODE_2
	Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) Data line 0 (SPIDAT[0]) selected for transmission. More...
#define	MCSPI_DATA_LINE_COMM_MODE_3
	Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) No transmission on Data Line 0 (SPIDAT[0]) More...
#define	MCSPI_DATA_LINE_COMM_MODE_4
	Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission Data Line 0 (SPIDAT[0]) selected for transmission. More...
#define	MCSPI_DATA_LINE_COMM_MODE_5
	Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission No transmission on Data Line 0 (SPIDAT[0]) More...
#define	MCSPI_DATA_LINE_COMM_MODE_6
	Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) Data line 0 (SPIDAT[0]) selected for transmission. More...
#define	MCSPI_DATA_LINE_COMM_MODE_7
	Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) No transmission on Data Line 0 (SPIDAT[0]) More...
#define	MCSPI_RX_FIFO_ENABLE
	McSPI peripheral Rx FIFO is enabled. More...
#define	MCSPI_RX_FIFO_DISABLE
	McSPI peripheral Rx FIFO is disabled. More...
#define	MCSPI_TX_FIFO_ENABLE
	McSPI peripheral Tx FIFO is enabled. More...
#define	MCSPI_TX_FIFO_DISABLE
	McSPI peripheral Tx FIFO is disabled. More...
#define	MCSPI_DMA_RX_EVENT
	McSPI peripheral read DMA event is enabled. More...
#define	MCSPI_DMA_TX_EVENT
	McSPI peripheral write DMA event is enabled. More...
#define	MCSPI_INT_TX_EMPTY(chan)
	Mask value of TX Empty interrupt enable of McSPI peripheral for the corresponding channel. More...
#define	MCSPI_INT_TX_UNDERFLOW(chan)
	Mask value of TX Underflow interrupt enable of McSPI peripheral for the corresponding channel. More...
#define	MCSPI_INT_RX_FULL(chan)
	Mask value of RX Full interrupt enable of McSPI peripheral for the corresponding channel. More...
#define	MCSPI_INT_RX0_OVERFLOW
	Mask value of RX Overflow interrupt status of McSPI peripheral. More...
#define	MCSPI_INT_EOWKE
	Mask value of End of word count interrupt enable of McSPI peripheral. More...
#define	MCSPI_INITDLY_0
	No delay is configured for first spi transfer from McSPI peripheral. More...
#define	MCSPI_INITDLY_4
	4 SPI bus clock delays is configured for first spi transfer from McSPI peripheral. More...
#define	MCSPI_INITDLY_8
	8 SPI bus clock delays is configured for first spi transfer from McSPI peripheral. More...
#define	MCSPI_INITDLY_16
	16 SPI bus clock delays is configured for first spi transfer from McSPI peripheral. More...
#define	MCSPI_INITDLY_32
	32 SPI bus clock delays is configured for first spi transfer from McSPI peripheral. More...
#define	MCSPI_CH_STAT_RXS_FULL
	McSPI channel status if Rx buffer is full. More...
#define	MCSPI_CH_STAT_TXS_EMPTY
	McSPI channel status if Tx buffer is empty. More...
#define	MCSPI_CH_STAT_EOT
	McSPI channel status if End of Transfer is completed. More...
#define	MCSPI_CH_TXFFE
	McSPI channel status if Tx FIFO buffer is empty. More...
#define	MCSPI_CH_TXFFF
	McSPI channel status if Tx FIFO buffer is full. More...
#define	MCSPI_CH_RXFFE
	McSPI channel status if Rx FIFO buffer is empty. More...
#define	MCSPI_CH_RXFFF
	McSPI channel status if Rx FIFO buffer is full. More...
#define	MCSPI_MOA_ENABLE
	Multiple word ocp access is enabled. More...
#define	MCSPI_MOA_DISABLE
	Multiple word ocp access is disabled. More...
#define	MCSPI_SINGLE_CH
	Single channel is configured for MCSPI Peripheral. More...
#define	MCSPI_MULTI_CH
	Multi channel is configured for MCSPI Peripheral. More...
#define	MCSPI_CS_POL_HIGH
	Chip select is held high during active state. More...
#define	MCSPI_CS_POL_LOW
	Chip select is held low during active state. More...
#define	MCSPI_FDAA_DISABLE
	FDAA operation of McSPI peripheral is disabled. More...
#define	MCSPI_FDAA_ENABLE
	FDAA operation of McSPI peripheral is enabled. More...
#define	MCSPI_CLOCKS_OCP_OFF_FUNC_OFF
	Both OCP and Functional clock is switched off. More...
#define	MCSPI_CLOCKS_OCP_ON_FUNC_OFF
	OCP clock is maintained but Functional clock is switched off. More...
#define	MCSPI_CLOCKS_OCP_OFF_FUNC_ON
	Functional clock is maintained but OCP clock is switched off. More...
#define	MCSPI_CLOCKS_OCP_ON_FUNC_ON
	Both OCP and Functional clock is maintained. More...
#define	MCSPI_SIDLEMODE_FORCE
	Force Idle Mode is requested for MCSPI peripheral. More...
#define	MCSPI_SIDLEMODE_NO
	No Idle Mode is requested for MCSPI peripheral. More...
#define	MCSPI_SIDLEMODE_SMART_IDLE
	Smart Idle Mode is requested for MCSPI peripheral. More...
#define	MCSPI_WAKEUP_ENABLE
	Wake-up feature control is enabled. More...
#define	MCSPI_WAKEUP_DISABLE
	Wake-up feature control is disabled. More...
#define	MCSPI_AUTOIDLE_ON
	Auromatic OCP clock gating is configured for MCSPI peripheral. More...
#define	MCSPI_AUTOIDLE_OFF
	OCP clock is configured as free running state for MCSPI peripheral. More...

Functions
void	McSPIClkConfig (uint32_t baseAddr, uint32_t spiInClk, uint32_t spiOutClk, uint32_t chNum, uint32_t clkMode)
	Configures the clock. More...
void	McSPIWordLengthSet (uint32_t baseAddr, uint32_t wordLength, uint32_t chNum)
	Configure the word length. More...
void	McSPICSEnable (uint32_t baseAddr)
	This API will enable the chip select pin. More...
void	McSPICSDisable (uint32_t baseAddr)
	This API will disable the chip select pin. More...
void	McSPICSPolarityConfig (uint32_t baseAddr, uint32_t spiEnPol, uint32_t chNum)
	This API will configure the chip select polarity. More...
void	McSPICSTimeControlSet (uint32_t baseAddr, uint32_t csTimeControl, uint32_t chNum)
	This API will configure the chip select time control. More...
static void	McSPICSAssert (uint32_t baseAddr, uint32_t chNum)
	This API will activate the chip select line. More...
static void	McSPICSDeAssert (uint32_t baseAddr, uint32_t chNum)
	This API will deactivate the chip select line. More...
void	McSPIStartBitEnable (uint32_t baseAddr, uint32_t chNum)
	This API will enable start bit. More...
void	McSPIStartBitPolarityConfig (uint32_t baseAddr, uint32_t startBitPol, uint32_t chNum)
	This API will configure the polarity of start bit. More...
void	McSPIStartBitDisable (uint32_t baseAddr, uint32_t chNum)
	This API will disable the start bit mode of McSPI peripheral. More...
void	McSPIMasterModeEnable (uint32_t baseAddr)
	This API will enable the McSPI controller in master mode. More...
void	McSPISlaveModeEnable (uint32_t baseAddr)
	This call will enable the McSPI controller in Slave mode. . More...
uint32_t	McSPIMasterModeConfig (uint32_t baseAddr, uint32_t channelMode, uint32_t trMode, uint32_t pinMode, uint32_t chNum)
	This API will enable the McSPI controller in master mode and configure other parameters required for master mode. More...
static void	McSPIChannelEnable (uint32_t baseAddr, uint32_t chNum)
	This API will enable the channel of McSPI controller. More...
static void	McSPIChannelDisable (uint32_t baseAddr, uint32_t chNum)
	This API will disable the channel of McSPI controller. More...
void	McSPIReset (uint32_t baseAddr)
	This API will reset the McSPI peripheral. More...
void	McSPITurboModeEnable (uint32_t baseAddr, uint32_t chNum)
	This API will enable the McSPI turbo mode of operation. More...
void	McSPITurboModeDisable (uint32_t baseAddr, uint32_t chNum)
	This API will disable the McSPI turbo mode of operation. More...
void	McSPITxFIFOConfig (uint32_t baseAddr, uint32_t txFifo, uint32_t chNum)
	This API will enable/disable the Tx FIFOs of McSPI peripheral. More...
void	McSPIRxFIFOConfig (uint32_t baseAddr, uint32_t rxFifo, uint32_t chNum)
	This API will enable/disable the Rx FIFOs of McSPI peripheral. More...
void	McSPIFIFOTrigLvlSet (uint32_t baseAddr, uint8_t afl, uint8_t ael, uint32_t trMode)
	This API will set the transfer levels used by FIFO depending on the various McSPI transmit/receive modes. More...
void	McSPIWordCountSet (uint32_t baseAddr, uint16_t wCnt)
	This API will set the McSPI word counter value. More...
void	McSPIDMAEnable (uint32_t baseAddr, uint32_t dmaFlags, uint32_t chNum)
	This API will enable the DMA read/write events of McSPI. More...
void	McSPIDMADisable (uint32_t baseAddr, uint32_t dmaFlags, uint32_t chNum)
	This API will disable the DMA read/write events of McSPI. More...
void	McSPIIntEnable (uint32_t baseAddr, uint32_t intFlags)
	This API will enable the McSPI Interrupts. More...
void	McSPIIntDisable (uint32_t baseAddr, uint32_t intFlags)
	This API will disable the McSPI Interrupts. More...
void	McSPIInitDelayConfig (uint32_t baseAddr, uint32_t initDelay)
	This API will set initial delay for first transfer from McSPI peripheral. More...
static void	McSPITransmitData (uint32_t baseAddr, uint32_t txData, uint32_t chNum)
	This API will put the data on to the McSPI Channel transmit register. More...
uint32_t	McSPIReceiveData (uint32_t baseAddr, uint32_t chNum)
	This API will return the data present in the MCSPI_RX register. More...
uint32_t	McSPIIntStatusGet (uint32_t baseAddr)
	This API will return the status of the McSPI peripheral interrupts. More...
void	McSPIIntStatusClear (uint32_t baseAddr, uint32_t intFlags)
	This API will clear the status of McSPI Interrupts. More...
static uint32_t	McSPIChannelStatusGet (uint32_t baseAddr, uint32_t chNum)
	This API will return the status of the McSPI channel currently in use. More...
void	McSPIMultipleWordAccessConfig (uint32_t baseAddr, uint32_t moa)
	This API will enable/disable multiple word OCP access for McSPI peripheral. More...
void	McSPIFIFODatManagementConfig (uint32_t baseAddr, uint32_t fdaa)
	This API will enable/disable the FIFO DMA address 256-bit aligned feature of McSPI peripheral. More...
void	MCSPISysConfigSetup (uint32_t baseAddr, uint32_t clockActivity, uint32_t sidleMode, uint32_t wakeUp, uint32_t autoIdle)
	MCSPISysConfigSetup() description for void MCSPISysConfigSetup(). This call will setup the SYSCONFIG register of the McSPI peripheral. More...
uint32_t	MCSPIPinDirSet (uint32_t baseAddr, uint32_t trMode, uint32_t pinMode, uint32_t chNum)
	MCSPIPinDirSet() description for void MCSPIPinDirSet(). This call will configure the Pin Direction and the transfer mode depending on the user sent values. More...
void	MCSPISingleChModeEnable (uint32_t baseAddr)
	MCSPISingleChModeEnable() description for void MCSPISingleChModeEnable(). This call will configure McSPI to work in single channel mode. More...
void	MCSPIMultiChModeEnable (uint32_t baseAddr)
	MCSPIMultiChModeEnable() description for void MCSPIMultiChModeEnable(). This call will configure McSPI to work in Multi channel mode. More...
void	McSPISetSlaveChipSel (uint32_t baseAddr, uint32_t chNum, uint32_t slaveChipSel)
	McSPISetSlaveChipSel() description for void McSPISetSlaveChipSel(). This call will activate the user specified chip select line. More...
static uint32_t	McSPIGetChannelCtrl (uint32_t baseAddr, uint32_t chNum)
	This API returns Channel control register value. More...
static void	McSPISetChannelCtrl (uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
	This API sets Channel control register value. More...
static uint32_t	McSPIGetChannelConf (uint32_t baseAddr, uint32_t chNum)
	This API returns Channel Config register value. More...
static void	McSPISetChannelConf (uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
	This API sets Channel Config register value. More...

Macro Definition Documentation

MCSPI_CLK_MODE_0

#define MCSPI_CLK_MODE_0

Value:

(((uint32_t) MCSPI_CH0CONF_POL_ACTIVEHIGH \
                                      << MCSPI_CH0CONF_POL_SHIFT) |           \
                                     MCSPI_CH0CONF_PHA_ODD)

McSPI clock Mode 0 is selected SPICLK is active high and sampling occurs on the rising edge.

MCSPI_CLK_MODE_1

#define MCSPI_CLK_MODE_1

Value:

(((uint32_t) MCSPI_CH0CONF_POL_ACTIVEHIGH \
                                      << MCSPI_CH0CONF_POL_SHIFT) |           \
                                     MCSPI_CH0CONF_PHA_EVEN)

McSPI clock Mode 1 is selected SPICLK is active high and sampling occurs on the falling edge.

MCSPI_CLK_MODE_2

#define MCSPI_CLK_MODE_2

Value:

(((uint32_t) MCSPI_CH0CONF_POL_ACTIVELOW << \
                                      MCSPI_CH0CONF_POL_SHIFT) |                \
                                     MCSPI_CH0CONF_PHA_ODD)

McSPI clock Mode 2 is selected SPICLK is active low and sampling occurs on the falling edge.

MCSPI_CLK_MODE_3

#define MCSPI_CLK_MODE_3

Value:

(((uint32_t) MCSPI_CH0CONF_POL_ACTIVELOW << \
                                      MCSPI_CH0CONF_POL_SHIFT) |                \
                                     MCSPI_CH0CONF_PHA_EVEN)

McSPI clock Mode 3 is selected SPICLK is active low and sampling occurs on the rising edge.

MCSPI_REG_OFFSET

#define MCSPI_REG_OFFSET   (0x14U)

McSPI Register Offset for MCSPI_CHxCONF, MCSPI_CHxSTAT, MCSPI_CHxCTRL, MCSPI_TXx and MCSPI_RXx register sets.

MCSPI_CHCONF

#define MCSPI_CHCONF

(

x

)

Value:

((uint32_t) MCSPI_CH0CONF + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

Base address of McSPI Channel configuration : MCSPI_CHCONF(x)

MCSPI_CHSTAT

#define MCSPI_CHSTAT

(

x

)

Value:

((uint32_t) MCSPI_CH0STAT + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

Base address of McSPI Channel status : McSPI_CHSTAT(x)

MCSPI_CHCTRL

#define MCSPI_CHCTRL

(

x

)

Value:

((uint32_t) MCSPI_CH0CTRL + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

Base address of McSPI_CHCTRL(x) which is used to enable channel.

MCSPI_CHTX

#define MCSPI_CHTX

(

x

)

Value:

((uint32_t) MCSPI_TX0 + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

Base address of McSPI_CHTX(x) which is used to store data to be transmitted.

MCSPI_CHRX

#define MCSPI_CHRX

(

x

)

Value:

((uint32_t) MCSPI_RX0 + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

Base address of McSPI_CHRX(x) which is used to store data to be received.

MCSPI_WORD_LENGTH_MIN

#define MCSPI_WORD_LENGTH_MIN   ((uint32_t) 4U)

Minumum word lengths that is valid for McSPI channel configuration.

MCSPI_WORD_LENGTH_MAX

#define MCSPI_WORD_LENGTH_MAX   ((uint32_t) 32U)

Maximum word lengths that is valid for McSPI channel configuration.

MCSPI_WORD_LENGTH

#define MCSPI_WORD_LENGTH

(

n

)

Value:

((((uint32_t) (n)) - \
                                      (uint32_t) 1U) << MCSPI_CH0CONF_WL_SHIFT)

Values used to set the word length for McSPI communication 'n' can take values only between 4 <= n <= 32.

MCSPI_CS_TCS_0PNT5_CLK

#define MCSPI_CS_TCS_0PNT5_CLK

Value:

((uint32_t) MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

chip select time control(TCS) configuration : Zero interface clock cycle between CS toggling and first or last edge of SPI clock

MCSPI_CS_TCS_1PNT5_CLK

#define MCSPI_CS_TCS_1PNT5_CLK

Value:

((uint32_t) MCSPI_CH0CONF_TCS0_ONECYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

chip select time control(TCS) configuration : One interface clock cycle between CS toggling and first or last edge of SPI clock

MCSPI_CS_TCS_2PNT5_CLK

#define MCSPI_CS_TCS_2PNT5_CLK

Value:

((uint32_t) MCSPI_CH0CONF_TCS0_TWOCYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

chip select time control(TCS) configuration : Two interface clock cycles between CS toggling and first or last edge of SPI clock

MCSPI_CS_TCS_3PNT5_CLK

#define MCSPI_CS_TCS_3PNT5_CLK

Value:

((uint32_t)                          \
                                     MCSPI_CH0CONF_TCS0_THREECYCLEDLY << \
                                     MCSPI_CH0CONF_TCS0_SHIFT)

chip select time control(TCS) configuration : Three interface clock cycles between CS toggling and first or last edge of SPI clock

MCSPI_START_BIT_POL_LOW

#define MCSPI_START_BIT_POL_LOW   (MCSPI_CH0CONF_SBPOL_LOWLEVEL)

Low polarity is set for start bit for McSPI communication.

MCSPI_START_BIT_POL_HIGH

#define MCSPI_START_BIT_POL_HIGH   (MCSPI_CH0CONF_SBPOL_HIGHLEVEL)

High polarity is set for start bit for McSPI communication.

MCSPI_TX_RX_MODE

#define MCSPI_TX_RX_MODE

Value:

((uint32_t) MCSPI_CH0CONF_TRM_TRANSRECEI << \
                                     MCSPI_CH0CONF_TRM_SHIFT)

Transmit-receive mode of McSPI peripheral in master mode is configured.

MCSPI_RX_ONLY_MODE

#define MCSPI_RX_ONLY_MODE

Value:

((uint32_t) MCSPI_CH0CONF_TRM_RECEIVONLY << \
                                     MCSPI_CH0CONF_TRM_SHIFT)

Only Receive mode of McSPI peripheral in master mode is configured.

MCSPI_TX_ONLY_MODE

#define MCSPI_TX_ONLY_MODE

Value:

((uint32_t) MCSPI_CH0CONF_TRM_TRANSONLY << \
                                     MCSPI_CH0CONF_TRM_SHIFT)

Only Transmit mode of McSPI peripheral in master mode is configured.

MCSPI_DATA_LINE_COMM_MODE_0

#define MCSPI_DATA_LINE_COMM_MODE_0

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission Data Line 0 (SPIDAT[0]) selected for transmission.

MCSPI_DATA_LINE_COMM_MODE_1

#define MCSPI_DATA_LINE_COMM_MODE_1

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED   \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission No transmission on Data Line 0 (SPIDAT[0])

MCSPI_DATA_LINE_COMM_MODE_2

#define MCSPI_DATA_LINE_COMM_MODE_2

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED   \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |           \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) Data line 0 (SPIDAT[0]) selected for transmission.

MCSPI_DATA_LINE_COMM_MODE_3

#define MCSPI_DATA_LINE_COMM_MODE_3

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<   \
                                       MCSPI_CH0CONF_IS_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |         \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 0 (SPIDAT[0]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) No transmission on Data Line 0 (SPIDAT[0])

MCSPI_DATA_LINE_COMM_MODE_4

#define MCSPI_DATA_LINE_COMM_MODE_4

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission Data Line 0 (SPIDAT[0]) selected for transmission.

MCSPI_DATA_LINE_COMM_MODE_5

#define MCSPI_DATA_LINE_COMM_MODE_5

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED   \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception Data line 1 (SPIDAT[1]) selected for transmission No transmission on Data Line 0 (SPIDAT[0])

MCSPI_DATA_LINE_COMM_MODE_6

#define MCSPI_DATA_LINE_COMM_MODE_6

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED   \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |           \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) Data line 0 (SPIDAT[0]) selected for transmission.

MCSPI_DATA_LINE_COMM_MODE_7

#define MCSPI_DATA_LINE_COMM_MODE_7

Value:

(((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<   \
                                        MCSPI_CH0CONF_IS_SHIFT) |              \
                                       ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED \
                                        << MCSPI_CH0CONF_DPE1_SHIFT) |         \
                                       ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED \
                                        << MCSPI_CH0CONF_DPE0_SHIFT))

Communication on Data line pins is configured as : Data line 1 (SPIDAT[1]) selected for reception No transmission on Data Line 1 (SPIDAT[1]) No transmission on Data Line 0 (SPIDAT[0])

MCSPI_RX_FIFO_ENABLE

#define MCSPI_RX_FIFO_ENABLE

Value:

((uint32_t) MCSPI_CH0CONF_FFER_FFENABLED \
                                      <<                                      \
                                      MCSPI_CH0CONF_FFER_SHIFT)

McSPI peripheral Rx FIFO is enabled.

MCSPI_RX_FIFO_DISABLE

#define MCSPI_RX_FIFO_DISABLE

Value:

((uint32_t) MCSPI_CH0CONF_FFER_FFDISABLED \
                                      << MCSPI_CH0CONF_FFER_SHIFT)

McSPI peripheral Rx FIFO is disabled.

MCSPI_TX_FIFO_ENABLE

#define MCSPI_TX_FIFO_ENABLE

Value:

((uint32_t) MCSPI_CH0CONF_FFEW_FFENABLED \
                                      << MCSPI_CH0CONF_FFEW_SHIFT)

McSPI peripheral Tx FIFO is enabled.

MCSPI_TX_FIFO_DISABLE

#define MCSPI_TX_FIFO_DISABLE

Value:

((uint32_t) MCSPI_CH0CONF_FFEW_FFDISABLED \
                                      << MCSPI_CH0CONF_FFEW_SHIFT)

McSPI peripheral Tx FIFO is disabled.

MCSPI_DMA_RX_EVENT

#define MCSPI_DMA_RX_EVENT

Value:

((uint32_t) MCSPI_CH0CONF_DMAR_ENABLED << \
                                      MCSPI_CH0CONF_DMAR_SHIFT)

McSPI peripheral read DMA event is enabled.

MCSPI_DMA_TX_EVENT

#define MCSPI_DMA_TX_EVENT

Value:

((uint32_t) MCSPI_CH0CONF_DMAW_ENABLED << \
                                      MCSPI_CH0CONF_DMAW_SHIFT)

McSPI peripheral write DMA event is enabled.

MCSPI_INT_TX_EMPTY

#define MCSPI_INT_TX_EMPTY

(

chan

)

Value:

((uint32_t)                               \
                                      MCSPI_IRQENABLE_TX0_EMPTY_ENABLE_MASK << \
                                      ((chan) * 4U))

Mask value of TX Empty interrupt enable of McSPI peripheral for the corresponding channel.

MCSPI_INT_TX_UNDERFLOW

#define MCSPI_INT_TX_UNDERFLOW

(

chan

)

Value:

((uint32_t)                                \
                                      MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE_MASK \
                                      << ((chan) * 4U))

Mask value of TX Underflow interrupt enable of McSPI peripheral for the corresponding channel.

MCSPI_INT_RX_FULL

#define MCSPI_INT_RX_FULL

(

chan

)

Value:

((uint32_t)                              \
                                      MCSPI_IRQENABLE_RX0_FULL_ENABLE_MASK << \
                                      ((chan) * 4U))

Mask value of RX Full interrupt enable of McSPI peripheral for the corresponding channel.

MCSPI_INT_RX0_OVERFLOW

#define MCSPI_INT_RX0_OVERFLOW

Value:

((uint32_t) \
                                      MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK)

Mask value of RX Overflow interrupt status of McSPI peripheral.

MCSPI_INT_EOWKE

#define MCSPI_INT_EOWKE

Value:

((uint32_t)                               \
                                      MCSPI_IRQENABLE_EOW_ENABLE_IRQENABLED << \
                                      MCSPI_IRQENABLE_EOW_ENABLE_SHIFT)

Mask value of End of word count interrupt enable of McSPI peripheral.

MCSPI_INITDLY_0

#define MCSPI_INITDLY_0

Value:

((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_NODELAY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

No delay is configured for first spi transfer from McSPI peripheral.

MCSPI_INITDLY_4

#define MCSPI_INITDLY_4

Value:

((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_4CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

4 SPI bus clock delays is configured for first spi transfer from McSPI peripheral.

MCSPI_INITDLY_8

#define MCSPI_INITDLY_8

Value:

((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_8CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

8 SPI bus clock delays is configured for first spi transfer from McSPI peripheral.

MCSPI_INITDLY_16

#define MCSPI_INITDLY_16

Value:

((uint32_t)                          \
                                      MCSPI_MODULCTRL_INITDLY_16CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

16 SPI bus clock delays is configured for first spi transfer from McSPI peripheral.

MCSPI_INITDLY_32

#define MCSPI_INITDLY_32

Value:

((uint32_t)                          \
                                      MCSPI_MODULCTRL_INITDLY_32CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

32 SPI bus clock delays is configured for first spi transfer from McSPI peripheral.

MCSPI_CH_STAT_RXS_FULL

#define MCSPI_CH_STAT_RXS_FULL

Value:

((uint32_t) MCSPI_CH0STAT_RXS_FULL << \
                                      MCSPI_CH0STAT_RXS_SHIFT)

McSPI channel status if Rx buffer is full.

MCSPI_CH_STAT_TXS_EMPTY

#define MCSPI_CH_STAT_TXS_EMPTY

Value:

((uint32_t) MCSPI_CH0STAT_TXS_EMPTY << \
                                      MCSPI_CH0STAT_TXS_SHIFT)

McSPI channel status if Tx buffer is empty.

MCSPI_CH_STAT_EOT

#define MCSPI_CH_STAT_EOT

Value:

((uint32_t) MCSPI_CH0STAT_EOT_COMPLETED << \
                                      MCSPI_CH0STAT_EOT_SHIFT)

McSPI channel status if End of Transfer is completed.

MCSPI_CH_TXFFE

#define MCSPI_CH_TXFFE

Value:

((uint32_t) MCSPI_CH0STAT_TXFFE_EMPTY << \
                                      MCSPI_CH0STAT_TXFFE_SHIFT)

McSPI channel status if Tx FIFO buffer is empty.

MCSPI_CH_TXFFF

#define MCSPI_CH_TXFFF

Value:

((uint32_t) MCSPI_CH0STAT_TXFFF_FULL << \
                                      MCSPI_CH0STAT_TXFFF_SHIFT)

McSPI channel status if Tx FIFO buffer is full.

MCSPI_CH_RXFFE

#define MCSPI_CH_RXFFE

Value:

((uint32_t) MCSPI_CH0STAT_RXFFE_EMPTY << \
                                      MCSPI_CH0STAT_RXFFE_SHIFT)

McSPI channel status if Rx FIFO buffer is empty.

MCSPI_CH_RXFFF

#define MCSPI_CH_RXFFF

Value:

((uint32_t) MCSPI_CH0STAT_RXFFF_FULL << \
                                      MCSPI_CH0STAT_RXFFF_SHIFT)

McSPI channel status if Rx FIFO buffer is full.

MCSPI_MOA_ENABLE

#define MCSPI_MOA_ENABLE

Value:

((uint32_t) MCSPI_MODULCTRL_MOA_MULTIACCES \
                                     << MCSPI_MODULCTRL_MOA_SHIFT)

Multiple word ocp access is enabled.

MCSPI_MOA_DISABLE

#define MCSPI_MOA_DISABLE

Value:

((uint32_t)                           \
                                     MCSPI_MODULCTRL_MOA_NOMULTIACCESS << \
                                     MCSPI_MODULCTRL_MOA_SHIFT)

Multiple word ocp access is disabled.

MCSPI_SINGLE_CH

#define MCSPI_SINGLE_CH

Value:

((uint32_t) MCSPI_MODULCTRL_SINGLE_SINGLE << \
                                    MCSPI_MODULCTRL_SINGLE_SHIFT)

Single channel is configured for MCSPI Peripheral.

MCSPI_MULTI_CH

#define MCSPI_MULTI_CH

Value:

((uint32_t) MCSPI_MODULCTRL_SINGLE_MULTI << \
                                   MCSPI_MODULCTRL_SINGLE_SHIFT)

Multi channel is configured for MCSPI Peripheral.

MCSPI_CS_POL_HIGH

#define MCSPI_CS_POL_HIGH

Value:

((uint32_t) MCSPI_CH0CONF_EPOL_ACTIVEHIGH << \
                                    MCSPI_CH0CONF_EPOL_SHIFT)

Chip select is held high during active state.

MCSPI_CS_POL_LOW

#define MCSPI_CS_POL_LOW

Value:

((uint32_t) MCSPI_CH0CONF_EPOL_ACTIVELOW << \
                                    MCSPI_CH0CONF_EPOL_SHIFT)

Chip select is held low during active state.

MCSPI_FDAA_DISABLE

#define MCSPI_FDAA_DISABLE

Value:

((uint32_t)                          \
                                      MCSPI_MODULCTRL_FDAA_SHADOWREGEN << \
                                      MCSPI_MODULCTRL_FDAA_SHIFT)

FDAA operation of McSPI peripheral is disabled.

MCSPI_FDAA_ENABLE

#define MCSPI_FDAA_ENABLE

Value:

((uint32_t)                          \
                                      MCSPI_MODULCTRL_FDAA_NOSHADOWREG << \
                                      MCSPI_MODULCTRL_FDAA_SHIFT)

FDAA operation of McSPI peripheral is enabled.

MCSPI_CLOCKS_OCP_OFF_FUNC_OFF

#define MCSPI_CLOCKS_OCP_OFF_FUNC_OFF

Value:

((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_NONE << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

Both OCP and Functional clock is switched off.

MCSPI_CLOCKS_OCP_ON_FUNC_OFF

#define MCSPI_CLOCKS_OCP_ON_FUNC_OFF

Value:

((uint32_t)                           \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_OCP << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

OCP clock is maintained but Functional clock is switched off.

MCSPI_CLOCKS_OCP_OFF_FUNC_ON

#define MCSPI_CLOCKS_OCP_OFF_FUNC_ON

Value:

((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_FUNC << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

Functional clock is maintained but OCP clock is switched off.

MCSPI_CLOCKS_OCP_ON_FUNC_ON

#define MCSPI_CLOCKS_OCP_ON_FUNC_ON

Value:

((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_BOTH << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

Both OCP and Functional clock is maintained.

MCSPI_SIDLEMODE_FORCE

#define MCSPI_SIDLEMODE_FORCE

Value:

((uint32_t)                         \
                                       MCSPI_SYSCONFIG_SIDLEMODE_FORCE << \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

Force Idle Mode is requested for MCSPI peripheral.

MCSPI_SIDLEMODE_NO

#define MCSPI_SIDLEMODE_NO

Value:

((uint32_t) MCSPI_SYSCONFIG_SIDLEMODE_NO \
                                       << MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

No Idle Mode is requested for MCSPI peripheral.

MCSPI_SIDLEMODE_SMART_IDLE

#define MCSPI_SIDLEMODE_SMART_IDLE

Value:

((uint32_t)                         \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SMART << \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

Smart Idle Mode is requested for MCSPI peripheral.

MCSPI_WAKEUP_ENABLE

#define MCSPI_WAKEUP_ENABLE

Value:

((uint32_t) MCSPI_SYSCONFIG_ENAWAKEUP_ON \
                                       << MCSPI_SYSCONFIG_ENAWAKEUP_SHIFT)

Wake-up feature control is enabled.

MCSPI_WAKEUP_DISABLE

#define MCSPI_WAKEUP_DISABLE

Value:

((uint32_t)                            \
                                       MCSPI_SYSCONFIG_ENAWAKEUP_NOWAKEUP << \
                                       MCSPI_SYSCONFIG_ENAWAKEUP_SHIFT)

Wake-up feature control is disabled.

MCSPI_AUTOIDLE_ON

#define MCSPI_AUTOIDLE_ON

Value:

((uint32_t) MCSPI_SYSCONFIG_AUTOIDLE_ON \
                                       << MCSPI_SYSCONFIG_AUTOIDLE_SHIFT)

Auromatic OCP clock gating is configured for MCSPI peripheral.

MCSPI_AUTOIDLE_OFF

#define MCSPI_AUTOIDLE_OFF

Value:

((uint32_t) MCSPI_SYSCONFIG_AUTOIDLE_OFF \
                                       << MCSPI_SYSCONFIG_AUTOIDLE_SHIFT)

OCP clock is configured as free running state for MCSPI peripheral.

Function Documentation

McSPIClkConfig()

void McSPIClkConfig	(	uint32_t	baseAddr,
		uint32_t	spiInClk,
		uint32_t	spiOutClk,
		uint32_t	chNum,
		uint32_t	clkMode
	)

Configures the clock.

This API will configure the clkD and extClk fields to generate required spi clock depending on the type of granularity. It will also set the phase and polarity of spiClk by the clkMode field.

Parameters

baseAddr	Memory Address of the McSPI instance used.
spiInClk	Clock frequency given to the McSPI module.
spiOutClk	Clock frequency on the McSPI bus.
chNum	Channel number of the McSPI instance used.
clkMode	Clock mode used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n 'clkMode' can take the following values.\n MCSPI_CLK_MODE_n - McSPI clock mode n.\n For clkMode 0 <= n <= 3.\n

Returns

none.

Note

: 1) clkMode depends on phase and polarity of McSPI clock.
2) To pass the desired value for clkMode please refer the McSPI_CH(i)CONF register.
3) Please understand the polarity and phase of the slave device connected and accordingly set the clkMode.
4) McSPIClkConfig does not have any significance in slave mode because the clock signal required for communication is generated by the master device.

McSPIWordLengthSet()

void McSPIWordLengthSet	(	uint32_t	baseAddr,
		uint32_t	wordLength,
		uint32_t	chNum
	)

Configure the word length.

This API will configure the length of McSPI word used for communication.

Parameters

baseAddr	Memory Address of the McSPI instance used.
wordLength	Length of a data word used for McSPI communication.
chNum	Channel number of the McSPI instance used. 'wordLength' can take the following values.\n MCSPI_WORD_LENGTH(n) - McSPI word length is n bits int32_t.\n For wordLength 4 <= n <= 32.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can vary from 0-3.\n

Returns

none.

Note

: wordLength can vary from 4-32 bits length. To program the required value of wordLength please refer the MCSPI_CH(i)CONF register.

McSPICSEnable()

void McSPICSEnable

(

uint32_t

baseAddr

)

This API will enable the chip select pin.

Parameters

baseAddr

Memory Address of the McSPI instance used.

Returns

none.

Note

: Modification of CS polarity, SPI clock phase and polarity is not allowed when CS is enabled.

McSPICSDisable()

void McSPICSDisable

(

uint32_t

baseAddr

)

This API will disable the chip select pin.

Parameters

baseAddr

Memory Address of the McSPI instance used.

Returns

none.

McSPICSPolarityConfig()

void McSPICSPolarityConfig	(	uint32_t	baseAddr,
		uint32_t	spiEnPol,
		uint32_t	chNum
	)

This API will configure the chip select polarity.

Parameters

baseAddr	Memory Address of the McSPI instance used.
spiEnPol	Polarity of CS line.
chNum	Channel number of the McSPI instance used. 'spiEnPol' can take the following values.\n MCSPI_CHnCONF_EPOL_ACTIVEHIGH - SPIEN pin is held high during the active state.\n MCSPI_CHnCONF_EPOL_ACTIVELOW - SPIEN pin is held low during the active state.\n where n is the channel number. 0 <= n <= 4 \n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPICSTimeControlSet()

void McSPICSTimeControlSet	(	uint32_t	baseAddr,
		uint32_t	csTimeControl,
		uint32_t	chNum
	)

This API will configure the chip select time control.

Parameters

baseAddr	Memory Address of the McSPI instance used.
csTimeControl	Chip Select time control.
chNum	Channel number of the McSPI instance used. 'csTimeControl' can take the following values.\n MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY\n MCSPI_CH0CONF_TCS0_ONECYCLEDLY\n MCSPI_CH0CONF_TCS0_TWOCYCLEDLY\n MCSPI_CH0CONF_TCS0_THREECYCLEDLY\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPICSAssert()

static void McSPICSAssert ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API will activate the chip select line.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPICSDeAssert()

static void McSPICSDeAssert ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API will deactivate the chip select line.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPIStartBitEnable()

void McSPIStartBitEnable	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

This API will enable start bit.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPIStartBitPolarityConfig()

void McSPIStartBitPolarityConfig	(	uint32_t	baseAddr,
		uint32_t	startBitPol,
		uint32_t	chNum
	)

This API will configure the polarity of start bit.

Parameters

baseAddr	Memory Address of the McSPI instance used.
startBitPol	Polarity of start bit.
chNum	Channel number of the McSPI instance used. 'startBitPol' can take the following values.\n MCSPI_START_BIT_POL_LOW - Polarity of start bit is held low during transmission.\n MCSPI_START_BIT_POL_HIGH - Polarity of start bit is held high during transmission.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPIStartBitDisable()

void McSPIStartBitDisable	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

This API will disable the start bit mode of McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPIMasterModeEnable()

void McSPIMasterModeEnable

(

uint32_t

baseAddr

)

This API will enable the McSPI controller in master mode.

Parameters

baseAddr

Memory Address of the McSPI instance used.

Returns

none.

McSPISlaveModeEnable()

void McSPISlaveModeEnable

(

uint32_t

baseAddr

)

This call will enable the McSPI controller in Slave mode.
.

Parameters

baseAddr

baseAddr of the McSPI instance used.

Returns

none.

McSPIMasterModeConfig()

uint32_t McSPIMasterModeConfig	(	uint32_t	baseAddr,
		uint32_t	channelMode,
		uint32_t	trMode,
		uint32_t	pinMode,
		uint32_t	chNum
	)

This API will enable the McSPI controller in master mode and configure other parameters required for master mode.

Parameters

baseAddr	Memory Address of the McSPI instance used.
channelMode	Single/Multi channel.
trMode	Transmit/Receive mode used in master configuration.
pinMode	Interface mode and pin assignment.
chNum	Channel number of the McSPI instance used. 'channelMode' can take the following values.\n MCSPI_MODULCTRL_SINGLE_SINGLE - Single channel mode is used.\n MCSPI_MODULCTRL_SINGLE_MULTI - Multi channel mode is used.\n 'trMode' can take the following values.\n MCSPI_TX_RX_MODE - Enable McSPI in TX and RX modes.\n MCSPI_RX_ONLY_MODE - Enable McSPI only in RX mode.\n MCSPI_TX_ONLY_MODE - Enable McSPI only in TX mode.\n 'pinMode' can take the following values.\n MCSPI_DATA_LINE_COMM_MODE_n - Mode n configuration for SPIDAT[1:0].\n For pinMode 0 <= n <= 7.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

'retVal' which states if the combination of trMode and pinMode chosen by the user is supported for communication on SPIDAT[1:0] pins.
TRUE - Communication supported by SPIDAT[1:0].
FALSE - Communication not supported by SPIDAT[1:0].

Note

Please refer the description about IS,DPE1,DPE0 and TRM bits for proper configuration of SPIDAT[1:0].

McSPIChannelEnable()

static void McSPIChannelEnable ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API will enable the channel of McSPI controller.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

Note

: Please ensure to enable only channel 0 in slave mode.
Channels other than 0 are not valid in slave mode.

McSPIChannelDisable()

static void McSPIChannelDisable ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API will disable the channel of McSPI controller.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPIReset()

void McSPIReset

(

uint32_t

baseAddr

)

This API will reset the McSPI peripheral.

Parameters

baseAddr

Memory Address of the McSPI instance used.

Returns

none.

McSPITurboModeEnable()

void McSPITurboModeEnable	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

This API will enable the McSPI turbo mode of operation.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

Note

McSPITurboModeDisable()

void McSPITurboModeDisable	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

This API will disable the McSPI turbo mode of operation.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

none.

McSPITxFIFOConfig()

void McSPITxFIFOConfig	(	uint32_t	baseAddr,
		uint32_t	txFifo,
		uint32_t	chNum
	)

This API will enable/disable the Tx FIFOs of McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
txFifo	FIFO used for transmit mode.
chNum	Channel number of the McSPI instance used. 'txFifo' can take the following values.\n MCSPI_TX_FIFO_ENABLE - Enables the transmitter FIFO of McSPI.\n MCSPI_TX_FIFO_DISABLE - Disables the transmitter FIFO of McSPI.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

Note

: Enabling FIFO is restricted to only 1 channel.

McSPIRxFIFOConfig()

void McSPIRxFIFOConfig	(	uint32_t	baseAddr,
		uint32_t	rxFifo,
		uint32_t	chNum
	)

This API will enable/disable the Rx FIFOs of McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
rxFifo	FIFO used for receive mode.
chNum	Channel number of the McSPI instance used. 'rxFifo' can take the following values.\n MCSPI_RX_FIFO_ENABLE - Enables the receiver FIFO of McSPI.\n MCSPI_RX_FIFO_DISABLE - Disables the receiver FIFO of McSPI.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

Note

: Enabling FIFO is restricted to only 1 channel.

McSPIFIFOTrigLvlSet()

void McSPIFIFOTrigLvlSet	(	uint32_t	baseAddr,
		uint8_t	afl,
		uint8_t	ael,
		uint32_t	trMode
	)

This API will set the transfer levels used by FIFO depending on the various McSPI transmit/receive modes.

Parameters

baseAddr	Memory Address of the McSPI instance used.
afl	Buffer almost full value.
ael	Buffer almost empty value.
trMode	Transmit/Receive modes used. 'trMode' can take the following values.\n MCSPI_TX_RX_MODE - Enable McSPI in TX and RX modes.\n MCSPI_RX_ONLY_MODE - Enable McSPI only in RX mode.\n MCSPI_TX_ONLY_MODE - Enable McSPI only in TX mode.\n

Returns

none.

Note

Values for afl and ael will have varying values depending on trMode. If trMode is MCSPI_TX_RX_MODE then afl and ael can take values ranging from 0-19. If trMode is MCSPI_RX_ONLY_MODE/ MCSPI_TX_ONLY_MODE then afl and ael can take values from 0-39.
While configuring mode of operation using trMode please ensure the same value of trMode is used while using API's McSPIMasterModeConfig and McSPISlaveModeConfig. Mismatch while using trMode for different APIs can result in unpredictable behaviour.
For 'ael' and 'afl' please send level values for both of the fields and do not send the value which has to be written into the register for the corresponding level value. For e.g. if 'ael' or 'afl' has to be 1 byte, then pass the parameter 'ael' or 'afl' as 1 and not 0 because the value which has to be written into register is manipulated inside the driver itself.

McSPIWordCountSet()

void McSPIWordCountSet	(	uint32_t	baseAddr,
		uint16_t	wCnt
	)

This API will set the McSPI word counter value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
wCnt	Word count.

Returns

none.

McSPIDMAEnable()

void McSPIDMAEnable	(	uint32_t	baseAddr,
		uint32_t	dmaFlags,
		uint32_t	chNum
	)

This API will enable the DMA read/write events of McSPI.

Parameters

baseAddr	Memory Address of the McSPI instance used.
dmaFlags	Variable used to enable DMA mode for Rx/Tx events.
chNum	Channel number of the McSPI instance used. 'dmaFlags' can take the following values.\n MCSPI_DMA_RX_EVENT - To enable DMA mode for Rx events.\n MCSPI_DMA_TX_EVENT - To enable DMA mode for Tx events.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

McSPIDMADisable()

void McSPIDMADisable	(	uint32_t	baseAddr,
		uint32_t	dmaFlags,
		uint32_t	chNum
	)

This API will disable the DMA read/write events of McSPI.

Parameters

baseAddr	Memory Address of the McSPI instance used.
dmaFlags	Variable used to disable DMA mode for Rx/Tx events.
chNum	Channel number of the McSPI instance used. 'dmaFlags' can take the following values.\n MCSPI_DMA_RX_EVENT - To disable DMA mode for Rx events.\n MCSPI_DMA_TX_EVENT - To disable DMA mode for Tx events.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

McSPIIntEnable()

void McSPIIntEnable	(	uint32_t	baseAddr,
		uint32_t	intFlags
	)

This API will enable the McSPI Interrupts.

Parameters

baseAddr	Memory Address of the McSPI instance used.
intFlags	Represents the various interrupts to be enabled.

Returns

none.

Note

Please ensure the proper channel number is passed while using the macros.

McSPIIntDisable()

void McSPIIntDisable	(	uint32_t	baseAddr,
		uint32_t	intFlags
	)

This API will disable the McSPI Interrupts.

Parameters

baseAddr

Memory Address of the McSPI instance used.

intFlags

Represents the various interrupts to be disabled. 'intFlags' can take the following values.\n MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty interrupt.\n MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow interrupt.\n MCSPI_INT_RX_FULL(chan) - Receiver register full interrupt.\n MCSPI_INT_RX0_OVERFLOW - Receiver register 0 overflow interrupt.\n MCSPI_INT_EOWKE - End of word count interrupt.\n 'chan' stands for channel number. Please specify the proper channel number while passing the macros. 0 <= chan <= 3 \n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

Note

Please ensure the proper channel number is passed while using the macros.

McSPIInitDelayConfig()

void McSPIInitDelayConfig	(	uint32_t	baseAddr,
		uint32_t	initDelay
	)

This API will set initial delay for first transfer from McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
initDelay	Delay used for first transfer. 'initDelay' can take the following values.\n MCSPI_INITDLY_0 - No delay for first transfer.\n MCSPI_INITDLY_4 - Delay of 4 SPI Clock.\n MCSPI_INITDLY_8 - Delay of 8 SPI Clock.\n MCSPI_INITDLY_16 - Delay of 16 SPI Clock.\n MCSPI_INITDLY_32 - Delay of 32 SPI Clock.\n

Returns

none.

Note

: Please note that this option is available only in single master mode.

McSPITransmitData()

static void McSPITransmitData ( uint32_t  baseAddr, uint32_t  txData, uint32_t  chNum  )

inlinestatic

This API will put the data on to the McSPI Channel transmit register.

Parameters

baseAddr	Memory Address of the McSPI instance used.
txData	32 bit data sent by the user which is put on to the MCSPI_TX register.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

none.

McSPIReceiveData()

uint32_t McSPIReceiveData	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

This API will return the data present in the MCSPI_RX register.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

Returns

This API will return the data received in the MCSPI_RX register.

McSPIIntStatusGet()

uint32_t McSPIIntStatusGet

(

uint32_t

baseAddr

)

This API will return the status of the McSPI peripheral interrupts.

Parameters

baseAddr

Memory Address of the McSPI instance used.

Returns

This API will return the status of the McSPI peripheral interrupts. User can use the following macros to check the status
MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty for channel n MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow for channel n
MCSPI_INT_RX_FULL(chan) - Receiver register full for channel n
MCSPI_INT_RX0_OVERFLOW - Receiver register overflow for channel 0
MCSPI_INT_EOWKE - End of word count interrupt
where 0 <= chan <= 3

McSPIIntStatusClear()

void McSPIIntStatusClear	(	uint32_t	baseAddr,
		uint32_t	intFlags
	)

This API will clear the status of McSPI Interrupts.

Parameters

baseAddr	Memory Address of the McSPI instance used.
intFlags	Represents the various interrupts to be cleared.

Returns

none.

Note

Please ensure the proper channel number is used while passing the macros passed.

McSPIChannelStatusGet()

static uint32_t McSPIChannelStatusGet ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API will return the status of the McSPI channel currently in use.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel used for communication. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n

Returns

This API will return the status of the McSPI channel status register. User can use the following macros to check the status
MCSPI_CH_STAT_RXS_FULL - Receiver register is full
MCSPI_CH_STAT_TXS_EMPTY - Transmitter register is full
MCSPI_CH_STAT_EOT - End of transfer status
MCSPI_CH_TXFFE - FIFO transmit buffer empty status
MCSPI_CH_TXFFF - FIFO transmit buffer full status
MCSPI_CH_RXFFE - FIFO receive buffer empty status
MCSPI_CH_RXFFF - FIFO receive buffer full status

McSPIMultipleWordAccessConfig()

void McSPIMultipleWordAccessConfig	(	uint32_t	baseAddr,
		uint32_t	moa
	)

This API will enable/disable multiple word OCP access for McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
moa	Used to enable/disable MOA in McSPI peripheral. 'moa' can take the following values.\n MCSPI_MOA_ENABLE - Enable MOA.\n MCSPI_MOA_DISABLE - Disable MOA.\n

Returns

none.

McSPIFIFODatManagementConfig()

void McSPIFIFODatManagementConfig	(	uint32_t	baseAddr,
		uint32_t	fdaa
	)

This API will enable/disable the FIFO DMA address 256-bit aligned feature of McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
fdaa	Used to enable/disable FDAA in McSPI peripheral. 'fdaa' can take the following values.\n MCSPI_FDAA_ENABLE - Enable FDAA.\n MCSPI_FDAA_DISABLE - Disable FDAA.\n

Returns

none.

MCSPISysConfigSetup()

void MCSPISysConfigSetup	(	uint32_t	baseAddr,
		uint32_t	clockActivity,
		uint32_t	sidleMode,
		uint32_t	wakeUp,
		uint32_t	autoIdle
	)

MCSPISysConfigSetup() description for void MCSPISysConfigSetup(). This call will setup the SYSCONFIG register of the McSPI peripheral.

Parameters

baseAddr	Memory Address of the McSPI instance used.
clockActivity	Clocks activity maintained during wake-up mode period.
sidleMode	Power management configuration.
wakeUp	Wake-up feature control.
autoIdle	Internal OCP Clock gating. 'clockActivity' can take the following values.\n MCSPI_CLOCKS_OCP_OFF_FUNC_OFF - OCP and functional clocks may be switched off.\n MCSPI_CLOCKS_OCP_ON_FUNC_OFF - OCP clock is maintained. Functional clock may be switched off.\n MCSPI_CLOCKS_OCP_OFF_FUNC_ON - Functional clock is maintained. OCP clock may be switched off.\n MCSPI_CLOCKS_OCP_ON_FUNC_ON - OCP and functional clocks are maintained.\n 'sidleMode' can take the following values.\n MCSPI_SIDLEMODE_FORCE MCSPI_SIDLEMODE_NO MCSPI_SIDLEMODE_SMART_IDLE 'wakeUp' can take the following values.\n MCSPI_WAKEUP_ENABLE - Wake-up capability is enabled.\n MCSPI_WAKEUP_DISABLE - Wake-up capability is disabled.\n 'autoIdle' can take the following values.\n MCSPI_AUTOIDLE_ON - Automatic OCP clock gating strategy applied.\n MCSPI_AUTOIDLE_OFF - OCP clock free-running.\n

Returns

none.

MCSPIPinDirSet()

uint32_t MCSPIPinDirSet	(	uint32_t	baseAddr,
		uint32_t	trMode,
		uint32_t	pinMode,
		uint32_t	chNum
	)

MCSPIPinDirSet() description for void MCSPIPinDirSet(). This call will configure the Pin Direction and the transfer mode depending on the user sent values.

Parameters

baseAddr	Memory Address of the McSPI instance used.
trMode	Transmit/Receive mode used in master configuration.
pinMode	Interface mode and pin assignment.
chNum	Channel number of the McSPI instance used. 'trMode' can take the following values.\n MCSPI_TX_RX_MODE - Enable McSPI in TX and RX modes.\n MCSPI_RX_ONLY_MODE - Enable McSPI only in RX mode.\n MCSPI_TX_ONLY_MODE - Enable McSPI only in TX mode.\n 'pinMode' can take the following values.\n MCSPI_DATA_LINE_COMM_MODE_n - Mode n configuration for SPIDAT[1:0].\n For pinMode 0 <= n <= 7.\n 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n

Returns

'retVal' which states if the combination of trMode and pinMode chosen by the user is supported for communication on SPIDAT[1:0] pins.
0 - Communication supported by SPIDAT[1:0].
1 - Communication not supported by SPIDAT[1:0].

Note

Please refer the description about IS,DPE1,DPE0 and TRM bits for proper configuration of SPIDAT[1:0].

MCSPISingleChModeEnable()

void MCSPISingleChModeEnable

(

uint32_t

baseAddr

)

MCSPISingleChModeEnable() description for void MCSPISingleChModeEnable(). This call will configure McSPI to work in single channel mode.

Parameters

baseAddr

Base address of the McSPI instance used.

MCSPIMultiChModeEnable()

void MCSPIMultiChModeEnable

(

uint32_t

baseAddr

)

MCSPIMultiChModeEnable() description for void MCSPIMultiChModeEnable(). This call will configure McSPI to work in Multi channel mode.

Parameters

baseAddr

Base address of the McSPI instance used.

McSPISetSlaveChipSel()

void McSPISetSlaveChipSel	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	slaveChipSel
	)

McSPISetSlaveChipSel() description for void McSPISetSlaveChipSel(). This call will activate the user specified chip select line.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
slaveChipSel	slave select signal detection. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum 0 <= n <= 3.\n 'slaveChipSel' can take the following values.\n MCSPI_SPIEN_0 - Detection enabled only on SPIEN[0].\n MCSPI_SPIEN_1 - Detection enabled only on SPIEN[1].\n MCSPI_SPIEN_2 - Detection enabled only on SPIEN[2].\n MCSPI_SPIEN_3 - Detection enabled only on SPIEN[3].\n

Returns

none.

McSPIGetChannelCtrl()

static uint32_t McSPIGetChannelCtrl ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API returns Channel control register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.

Returns

Channel control register value.

McSPISetChannelCtrl()

static void McSPISetChannelCtrl ( uint32_t  baseAddr, uint32_t  chNum, uint32_t  regVal  )

inlinestatic

This API sets Channel control register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
regVal	register value to set in channel control register.

Returns

none.

McSPIGetChannelConf()

static uint32_t McSPIGetChannelConf ( uint32_t  baseAddr, uint32_t  chNum  )

inlinestatic

This API returns Channel Config register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.

Returns

Channel Config register value.

McSPISetChannelConf()

static void McSPISetChannelConf ( uint32_t  baseAddr, uint32_t  chNum, uint32_t  regVal  )

inlinestatic

This API sets Channel Config register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
regVal	register value to set in channel Config register.

Returns

none.