PDK API Guide for J721E
csl_gpioAux.h
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1 
48 #ifndef CSL_GPIOAUX_H
49 #define CSL_GPIOAUX_H
50 
51 #include <ti/csl/csl_gpio.h>
52 
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56 
105 /*for misra warning*/
106 static inline void CSL_GPIO_getPID
107 (
108  CSL_GpioHandle hGpio,
109  Uint8 *scheme,
110  Uint16 *function,
111  Uint8 *rtl,
112  Uint8 *major,
113  Uint8 *custom,
114  Uint8 *minor
115 );
116 static inline void CSL_GPIO_getPID
117 (
118  CSL_GpioHandle hGpio,
119  Uint8 *scheme,
120  Uint16 *function,
121  Uint8 *rtl,
122  Uint8 *major,
123  Uint8 *custom,
124  Uint8 *minor
125 )
126 {
127  Uint32 value = hGpio->PID;
128 
129  *scheme = (Uint8)CSL_FEXT (value, GPIO_PID_SCHEME);
130  *function = (Uint16)CSL_FEXT (value, GPIO_PID_FUNC);
131  *rtl = (Uint8)CSL_FEXT (value, GPIO_PID_RTL);
132  *major = (Uint8)CSL_FEXT (value, GPIO_PID_MAJOR);
133  *custom = (Uint8)CSL_FEXT (value, GPIO_PID_CUSTOM);
134  *minor = (Uint8)CSL_FEXT (value, GPIO_PID_MINOR);
135 }
136 
180 /*for misra warning*/
181 static inline void CSL_GPIO_getPCR
182 (
183  CSL_GpioHandle hGpio,
184  Uint8 *soft,
185  Uint8 *free
186 );
187 static inline void CSL_GPIO_getPCR
188 (
189  CSL_GpioHandle hGpio,
190  Uint8 *soft,
191  Uint8 *free
192 )
193 {
194  Uint32 value = hGpio->PCR;
195  *soft = (Uint8)CSL_FEXT (value, GPIO_PCR_SOFT);
196  *free = (Uint8)CSL_FEXT (value, GPIO_PCR_FREE);
197 }
198 
237 /*for misra warning*/
238 static inline void CSL_GPIO_bankInterruptEnable
239 (
240  CSL_GpioHandle hGpio,
241  Uint8 bankNum
242 );
243 static inline void CSL_GPIO_bankInterruptEnable
244 (
245  CSL_GpioHandle hGpio,
246  Uint8 bankNum
247 )
248 {
249  CSL_FINSR (hGpio->BINTEN, bankNum, bankNum, 1U);
250  return;
251 }
252 
291 /*for misra warning*/
292 static inline void CSL_GPIO_bankInterruptDisable
293 (
294  CSL_GpioHandle hGpio,
295  Uint8 bankNum
296 );
297 static inline void CSL_GPIO_bankInterruptDisable
298 (
299  CSL_GpioHandle hGpio,
300  Uint8 bankNum
301 )
302 {
303  CSL_FINSR (hGpio->BINTEN, bankNum, bankNum, 0U);
304  return;
305 }
306 
352 /*for misra warning*/
353 static inline Bool CSL_GPIO_isBankInterruptEnabled
354 (
355  CSL_GpioHandle hGpio,
356  Uint8 bankNum
357 );
358 static inline Bool CSL_GPIO_isBankInterruptEnabled
359 (
360  CSL_GpioHandle hGpio,
361  Uint8 bankNum
362 )
363 {
364  Bool ret_val;
365  if (CSL_FEXTR (hGpio->BINTEN, (Uint32)bankNum, (Uint32)bankNum) == 1U)
366  {
367  ret_val = TRUE;
368  }
369  else
370  {
371  ret_val = FALSE;
372  }
373  return ret_val;
374 }
375 
414 /*for misra warning*/
415 static inline void CSL_GPIO_setPinDirOutput
416 (
417  CSL_GpioHandle hGpio,
418  Uint8 pinNum
419 );
420 static inline void CSL_GPIO_setPinDirOutput
421 (
422  CSL_GpioHandle hGpio,
423  Uint8 pinNum
424 )
425 {
426  Uint8 bankIndex, bitPos;
427 
428  bankIndex = pinNum / 32U;
429  bitPos = pinNum % 32U;
430 
431  CSL_FINSR (hGpio->BANK_REGISTERS[bankIndex].DIR, bitPos, bitPos, 0U);
432  return;
433 }
434 
473 /*for misra warning*/
474 static inline void CSL_GPIO_setPinDirInput
475 (
476  CSL_GpioHandle hGpio,
477  Uint8 pinNum
478 );
479 static inline void CSL_GPIO_setPinDirInput
480 (
481  CSL_GpioHandle hGpio,
482  Uint8 pinNum
483 )
484 {
485  Uint8 bankIndex, bitPos;
486 
487  bankIndex = pinNum / 32U;
488  bitPos = pinNum % 32U;
489  CSL_FINSR (hGpio->BANK_REGISTERS[bankIndex].DIR, bitPos, bitPos, 1U);
490  return;
491 }
492 
539 /*for misra warning*/
540 static inline Bool CSL_GPIO_getPinDirection
541 (
542  CSL_GpioHandle hGpio,
543  Uint8 pinNum
544 );
545 static inline Bool CSL_GPIO_getPinDirection
546 (
547  CSL_GpioHandle hGpio,
548  Uint8 pinNum
549 )
550 {
551  Uint32 bankIndex, bitPos;
552 
553  bankIndex = (Uint32)pinNum / 32U;
554  bitPos = (Uint32)pinNum % 32U;
555 
556  return ((Bool)(CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].DIR, bitPos, bitPos)));
557 }
558 
598 /*for misra warning*/
599 static inline void CSL_GPIO_getOutputData
600 (
601  CSL_GpioHandle hGpio,
602  Uint8 pinNum,
603  Uint8 *outData
604 );
605 static inline void CSL_GPIO_getOutputData
606 (
607  CSL_GpioHandle hGpio,
608  Uint8 pinNum,
609  Uint8 *outData
610 )
611 {
612  Uint32 bankIndex, bitPos;
613 
614  bankIndex = (Uint32)pinNum / 32U;
615  bitPos = (Uint32)pinNum % 32U;
616 
617  *outData = (Uint8)CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].OUT_DATA, bitPos, bitPos);
618  return;
619 }
620 
659 /*for misra warning*/
660 static inline void CSL_GPIO_setOutputData
661 (
662  CSL_GpioHandle hGpio,
663  Uint8 pinNum
664 );
665 static inline void CSL_GPIO_setOutputData
666 (
667  CSL_GpioHandle hGpio,
668  Uint8 pinNum
669 )
670 {
671  Uint8 bankIndex, bitPos;
672 
673  bankIndex = pinNum / 32U;
674  bitPos = pinNum % 32U;
675 
676  hGpio->BANK_REGISTERS[bankIndex].SET_DATA = (1U) << bitPos;
677  return;
678 }
679 
718 /*for misra warning*/
719 static inline void CSL_GPIO_clearOutputData
720 (
721  CSL_GpioHandle hGpio,
722  Uint8 pinNum
723 );
724 static inline void CSL_GPIO_clearOutputData
725 (
726  CSL_GpioHandle hGpio,
727  Uint8 pinNum
728 )
729 {
730  Uint8 bankIndex, bitPos;
731 
732  bankIndex = pinNum / 32U;
733  bitPos = pinNum % 32U;
734 
735  hGpio->BANK_REGISTERS[bankIndex].CLR_DATA = (1U) << bitPos;
736 
737  return;
738 }
739 
779 /*for misra warning*/
780 static inline void CSL_GPIO_getInputData
781 (
782  CSL_GpioHandle hGpio,
783  Uint8 pinNum,
784  Uint8 *inData
785 );
786 static inline void CSL_GPIO_getInputData
787 (
788  CSL_GpioHandle hGpio,
789  Uint8 pinNum,
790  Uint8 *inData
791 )
792 {
793  Uint32 bankIndex, bitPos;
794 
795  bankIndex = (Uint32)pinNum / 32U;
796  bitPos = (Uint32)pinNum % 32U;
797 
798  *inData = (Uint8)CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].IN_DATA, bitPos, bitPos);
799  return;
800 }
801 
840 /*for misra warning*/
841 static inline void CSL_GPIO_setRisingEdgeDetect
842 (
843  CSL_GpioHandle hGpio,
844  Uint8 pinNum
845 );
846 static inline void CSL_GPIO_setRisingEdgeDetect
847 (
848  CSL_GpioHandle hGpio,
849  Uint8 pinNum
850 )
851 {
852  Uint8 bankIndex, bitPos;
853 
854  bankIndex = pinNum / 32U;
855  bitPos = pinNum % 32U;
856 
857  CSL_FINSR (hGpio->BANK_REGISTERS[bankIndex].SET_RIS_TRIG, bitPos, bitPos, 1U);
858  return;
859 }
860 
899 /*for misra warning*/
900 static inline void CSL_GPIO_clearRisingEdgeDetect
901 (
902  CSL_GpioHandle hGpio,
903  Uint8 pinNum
904 );
905 static inline void CSL_GPIO_clearRisingEdgeDetect
906 (
907  CSL_GpioHandle hGpio,
908  Uint8 pinNum
909 )
910 {
911  Uint8 bankIndex;
912 
913  bankIndex = pinNum / 32U;
914 
915  hGpio->BANK_REGISTERS[bankIndex].CLR_RIS_TRIG = (1U) << pinNum;
916  return;
917 }
918 
965 /*for misra warning*/
966 static inline Bool CSL_GPIO_isRisingEdgeDetect
967 (
968  CSL_GpioHandle hGpio,
969  Uint8 pinNum
970 );
971 static inline Bool CSL_GPIO_isRisingEdgeDetect
972 (
973  CSL_GpioHandle hGpio,
974  Uint8 pinNum
975 )
976 {
977  Uint32 bankIndex, bitPos;
978  Bool ret_val;
979  bankIndex = (Uint32)pinNum / 32U;
980  bitPos = (Uint32)pinNum % 32U;
981 
982  if (CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].SET_RIS_TRIG, bitPos, bitPos) == 1U)
983  {
984  ret_val = TRUE;
985  }
986  else
987  {
988  ret_val = FALSE;
989  }
990  return ret_val;
991 }
992 
1031 /*for misra warning*/
1032 static inline void CSL_GPIO_setFallingEdgeDetect
1033 (
1034  CSL_GpioHandle hGpio,
1035  Uint8 pinNum
1036 );
1037 static inline void CSL_GPIO_setFallingEdgeDetect
1038 (
1039  CSL_GpioHandle hGpio,
1040  Uint8 pinNum
1041 )
1042 {
1043  Uint8 bankIndex, bitPos;
1044 
1045  bankIndex = pinNum / 32U;
1046  bitPos = pinNum % 32U;
1047 
1048  CSL_FINSR (hGpio->BANK_REGISTERS[bankIndex].SET_FAL_TRIG, bitPos, bitPos, 1U);
1049  return;
1050 }
1051 
1090 /*for misra warning*/
1091 static inline void CSL_GPIO_clearFallingEdgeDetect
1092 (
1093  CSL_GpioHandle hGpio,
1094  Uint8 pinNum
1095 );
1096 static inline void CSL_GPIO_clearFallingEdgeDetect
1097 (
1098  CSL_GpioHandle hGpio,
1099  Uint8 pinNum
1100 )
1101 {
1102  Uint8 bankIndex;
1103 
1104  bankIndex = pinNum / 32U;
1105 
1106  hGpio->BANK_REGISTERS[bankIndex].CLR_FAL_TRIG = (1U) << pinNum;
1107  return;
1108 }
1109 
1156 /*for misra warning*/
1157 static inline Bool CSL_GPIO_isFallingEdgeDetect
1158 (
1159  CSL_GpioHandle hGpio,
1160  Uint8 pinNum
1161 );
1162 static inline Bool CSL_GPIO_isFallingEdgeDetect
1163 (
1164  CSL_GpioHandle hGpio,
1165  Uint8 pinNum
1166 )
1167 {
1168  Uint32 bankIndex, bitPos;
1169  Bool ret_val;
1170  bankIndex = (Uint32)pinNum / 32U;
1171  bitPos = (Uint32)pinNum % 32U;
1172 
1173  if (CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].SET_FAL_TRIG, bitPos, bitPos) == 1U)
1174  {
1175  ret_val = TRUE;
1176  }
1177  else
1178  {
1179  ret_val = FALSE;
1180  }
1181  return ret_val;
1182 }
1183 
1230 /*for misra warning*/
1231 static inline Bool CSL_GPIO_getInterruptStatus
1232 (
1233  CSL_GpioHandle hGpio,
1234  Uint8 pinNum
1235 );
1236 static inline Bool CSL_GPIO_getInterruptStatus
1237 (
1238  CSL_GpioHandle hGpio,
1239  Uint8 pinNum
1240 )
1241 {
1242  Uint32 bankIndex, bitPos;
1243 
1244  bankIndex = (Uint32)pinNum / 32U;
1245  bitPos = (Uint32)pinNum % 32U;
1246 
1247  return ((Bool)(CSL_FEXTR (hGpio->BANK_REGISTERS[bankIndex].INTSTAT, bitPos, bitPos)));
1248 }
1249 
1291 /*for misra warning*/
1292 static inline void CSL_GPIO_clearInterruptStatus
1293 (
1294  CSL_GpioHandle hGpio,
1295  Uint8 pinNum
1296 );
1297 static inline void CSL_GPIO_clearInterruptStatus
1298 (
1299  CSL_GpioHandle hGpio,
1300  Uint8 pinNum
1301 )
1302 {
1303  Uint8 bankIndex;
1304 
1305  bankIndex = pinNum / 32U;
1306 
1307  hGpio->BANK_REGISTERS[bankIndex].INTSTAT = (1U) << pinNum;
1308  return;
1309 }
1310 
1315 #ifdef __cplusplus
1316 }
1317 #endif
1318 
1319 #endif /* CSL_GPIOAUX_H */
1320 
CSL_GPIO_bankInterruptDisable
static void CSL_GPIO_bankInterruptDisable(CSL_GpioHandle hGpio, Uint8 bankNum)
Definition: csl_gpioAux.h:298
CSL_GPIO_clearOutputData
static void CSL_GPIO_clearOutputData(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:725
TRUE
#define TRUE
Definition: csl_types.h:54
CSL_GPIO_isRisingEdgeDetect
static Bool CSL_GPIO_isRisingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:972
CSL_GPIO_setPinDirOutput
static void CSL_GPIO_setPinDirOutput(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:421
FALSE
#define FALSE
Definition: csl_types.h:55
CSL_GPIO_setRisingEdgeDetect
static void CSL_GPIO_setRisingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:847
CSL_GPIO_bankInterruptEnable
static void CSL_GPIO_bankInterruptEnable(CSL_GpioHandle hGpio, Uint8 bankNum)
Definition: csl_gpioAux.h:244
value
uint32_t value
Definition: tisci_otp_revision.h:199
CSL_GPIO_clearRisingEdgeDetect
static void CSL_GPIO_clearRisingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:906
CSL_GPIO_isBankInterruptEnabled
static Bool CSL_GPIO_isBankInterruptEnabled(CSL_GpioHandle hGpio, Uint8 bankNum)
Definition: csl_gpioAux.h:359
CSL_GPIO_isFallingEdgeDetect
static Bool CSL_GPIO_isFallingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:1163
CSL_GPIO_getPID
static void CSL_GPIO_getPID(CSL_GpioHandle hGpio, Uint8 *scheme, Uint16 *function, Uint8 *rtl, Uint8 *major, Uint8 *custom, Uint8 *minor)
Definition: csl_gpioAux.h:117
CSL_GPIO_getInterruptStatus
static Bool CSL_GPIO_getInterruptStatus(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:1237
CSL_GPIO_getPCR
static void CSL_GPIO_getPCR(CSL_GpioHandle hGpio, Uint8 *soft, Uint8 *free)
Definition: csl_gpioAux.h:188
CSL_GPIO_getPinDirection
static Bool CSL_GPIO_getPinDirection(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:546
CSL_GPIO_clearInterruptStatus
static void CSL_GPIO_clearInterruptStatus(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:1298
CSL_GPIO_getOutputData
static void CSL_GPIO_getOutputData(CSL_GpioHandle hGpio, Uint8 pinNum, Uint8 *outData)
Definition: csl_gpioAux.h:606
CSL_GPIO_getInputData
static void CSL_GPIO_getInputData(CSL_GpioHandle hGpio, Uint8 pinNum, Uint8 *inData)
Definition: csl_gpioAux.h:787
CSL_GPIO_setOutputData
static void CSL_GPIO_setOutputData(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:666
CSL_GPIO_clearFallingEdgeDetect
static void CSL_GPIO_clearFallingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:1097
CSL_GPIO_setPinDirInput
static void CSL_GPIO_setPinDirInput(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:480
CSL_GPIO_setFallingEdgeDetect
static void CSL_GPIO_setFallingEdgeDetect(CSL_GpioHandle hGpio, Uint8 pinNum)
Definition: csl_gpioAux.h:1038