Introduction

This files defines ETH MCAL configuration structures

Data Structures
struct	Eth_CpswConfigType
	Eth Cpsw Configurations type Configuration related to Cpsw data. More...

struct	Eth_Udma_RingCfgType
	Eth Udma ring Configurations type Configuration related to Udma ring. More...

struct	Eth_Udma_ProxyCfgType
	Eth Udma Proxy Configurations type Configuration related to Udma proxy. More...

struct	Eth_Udma_EventCfgType
	Eth Udma event Configurations type Configuration related to Udma event. More...

struct	Eth_Udma_RingEventCfgType
	Eth ring event configuration type Configuration related to ring event. More...

struct	Eth_FifoRingMapCfgType
	Eth Fifo ring map configuration type Configuration related to fifo map to ring. More...

struct	Eth_ChannelCfgType
	Eth channel configuration type Configuration related to channel. More...

struct	Eth_FlowCfgType
	Eth flow configuration type Configuration related to flow. More...

struct	Eth_ChannelFlowCfgType
	Eth channel flow configuration type Configuration related to channel flow. More...

struct	Eth_FifoHandleType
	Eth Fifo configuration type Configuration related to Fifo. More...

struct	Eth_Udma_CfgType
	Eth Udma configuration type Configuration related to Udma. More...

struct	Eth_VirtualMacConfigType
	Eth driver virtual mac configuration data Configuration related to virtual MAC configuration. More...

struct	Eth_HwTimerConfigType
	Eth driver hardware timer configuration data Configuration related to hardware timer. More...

struct	Eth_ControlerConfigType
	Eth controller configuration type Configuration related to Eth controller configuration. More...

struct	Eth_ConfigType
	Eth configuration type Configuration data of all controller. More...

Functions
	VAR (uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U]

	VAR (Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[16U]

	VAR (uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[16U]

	VAR (Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U]

	VAR (Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U]

Std_ReturnType	AppUtils_EthRingCfg (uint8 ctrlIdx, uint8 Id)

Variables
const Eth_Udma_RingCfgType	Eth_Udma_RingCfg_0 [6U]

const Eth_Udma_EventCfgType	Eth_EventCfg_Ctrl_0 [2U]

const Eth_Udma_RingEventCfgType	Eth_RingEventCfg_Ctrl_0 [2U]

Typedefs
typedef void(*	Eth_RpcCmdComplete) (uint8 CtrlIdx, uint8 sid, sint32 status)
	Application callback to indicate Rpc dispatch command completion. More...

typedef void(*	Eth_RpcFwRegistered) (uint8 CtrlIdx)
	Application callback to indicate Ethernet firmware registered with the Eth RPC client. More...

typedef Std_ReturnType(*	Eth_DmaRingCfg) (uint8 ctrlIdx, uint8 ringIdx)

Enumerations
enum	Eth_PortType { ETH_PORT_HOST_PORT = 0x00U, ETH_MAC_PORT_FIRST = 0x01U, ETH_PORT_MAC_PORT_1 = 0x01U, ETH_PORT_MAC_PORT_2 = 0x02U, ETH_PORT_MAC_PORT_3 = 0x03U, ETH_PORT_MAC_PORT_4 = 0x04U, ETH_PORT_MAC_PORT_5 = 0x05U, ETH_PORT_MAC_PORT_6 = 0x06U, ETH_PORT_MAC_PORT_7 = 0x07U, ETH_PORT_MAC_PORT_8 = 0x08U, ETH_PORT_MAC_PORT_LAST = ETH_PORT_MAC_PORT_8 }
	Port identifier. More...

enum	Eth_MacConnectionType { ETH_MAC_CONN_TYPE_RMII_10 = 0x01U, ETH_MAC_CONN_TYPE_RMII_100 = 0x02U, ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF = 0x03U, ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL = 0x04U, ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL = 0x05U, ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND = 0x06U }
	Type/Speed/Duplex connection type. More...

enum	Eth_EnetType { ETH_ENETTYPE_CPSW2G = 0x00U, ETH_ENETTYPE_CPSW9G = 0x01U, ETH_ENETTYPE_CPSW5G = 0x02U, ETH_ENETTYPE_CPSW3G = 0x03U, ETH_ENETTYPE_CPSWLAST }
	Enet Cpsw Type identifier. More...

enum	Eth_MdioOperModeType { ETH_MDIO_OPMODE_NORMAL = 0x00U, ETH_MDIO_OPMODE_MANUAL = 0x01U }
	MDIO operating mode. More...

Macros
#define	ETH_VERSION_INFO_API (STD_ON)
	Enable/disable SPI get version info API. More...

#define	ETH_GLOBALTIMESUPPORT_API (STD_ON)
	Enable/disable Eth time sync related API. More...

#define	ETH_DEV_ERROR_DETECT (STD_ON)
	Enable/disable Development Error Detection. More...

#define	ETH_GET_COUNTER_VALUES_API (STD_ON)
	Enable/disable Eth get counter values API. More...

#define	ETH_GET_RX_STATS_API (STD_ON)
	Enable/disable Eth get RX stats count API. More...

#define	ETH_GET_TX_STATS_API (STD_ON)
	Enable/disable Eth get TX stats count API. More...

#define	ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON)
	Enable/disable Eth get TX error stats count API. More...

#define	ETH_ZERO_COPY_API (STD_OFF)
	Enable/disable Eth Zero-Copy support related APIs. More...

#define	ETH_HEADER_ACCESS_API (STD_OFF)
	Enable/disable Eth Tx/Rx Header Access related APIs. More...

#define	ETH_TRAFFIC_SHAPING_API (STD_OFF)
	Enable/disable Eth Traffic Shaping related APIs. More...

#define	ETH_GET_COUNTER_STATE_API (STD_OFF)
	Enable/disable Eth get Counter state API. More...

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF)
	Enable/disable Hardware Offloading for ICMP checksums. More...

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF)
	Enable/disable Hardware offloading for IPv4 Header checksums. More...

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF)
	Enable/disable Hardware offloading for TCP checksums. More...

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF)
	Enable/disable Hardware offloading for UDP checksums. More...

#define	ETH_ENABLE_MII_API (STD_ON)
	Enable/disable Eth MII related API. More...

#define	ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON)
	Enable/disable optional API Eth_UpdatePhysAddrFilter. More...

#define	ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF)
	Enable/disable optional API Eth_NotifyVirtmacMsgReceived. More...

#define	ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic. More...

#define	ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic. More...

#define	ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac. More...

#define	ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac. More...

#define	ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr. More...

#define	ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr. More...

#define	ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr. More...

#define	ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr. More...

#define	ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDelAddr. More...

#define	ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF)
	Enable/disable optional API Eth_SendCustomNotify. More...

#define	ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAddVlan. More...

#define	ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDelVlan. More...

#define	ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h"
	EthIf Callback Header File to include inside the Eth driver. More...

#define	ETH_ISR_TYPE (ETH_ISR_CAT2)
	ISR type. More...

#define	ETH_OS_COUNTER_ID ((CounterType)OsCounter_0)
	Counter ID for counter used to count wait ticks. More...

#define	ETH_OS_COUNTER_FREQ (1000000000U)
	Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID. More...

#define	ETH_INVALID_RING_ID (0xFFFFU)
	Eth Invalid Ring Id value. More...

#define	ETH_INVALID_EVENT_ID (0xFFFFU)
	Eth Invalid Event Id value. More...

#define	ETH_INVALID_CHAN_ID (0xFFFFU)
	Eth Invalid channel Id. More...

#define	ETH_INVALID_FLOW_ID (0xFFFFU)
	Eth Invalid Flow Id. More...

#define	ETH_INVALID_IRQ_ID (0xFFFFU)
	Eth Invalid IRQ value. More...

#define	ETH_DEM_NO_EVENT (0xFFFFU)
	Eth invalid DEM event ID. More...

#define	ETH_VIRTUALMAC_SUPPORT (STD_OFF)
	Enable/disable Virtual MAC support. More...

#define	ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U)
	Timeout value for Firmware Attach msg received from server. More...

#define	EthConf_EthCtrlConfig_EthConfig_0 (0U)
	Eth controller ID Configured controller ID(s) More...

#define	ETH_CTRL_ID_MAX (1u)
	Eth max controller ID. More...

#define	UDMA_WAIT_TEARDOWN_COUNTER (10000u)
	Eth DMA max teardown timeout. More...

#define	ETH_START_SEC_CONST_UNSPECIFIED

#define	ETH_STOP_SEC_CONST_UNSPECIFIED

#define	ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define	ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define	ETH_START_SEC_VAR_NO_INIT_8

#define	ETH_STOP_SEC_VAR_NO_INIT_8

#define	ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

#define	ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

#define	ETH_START_SEC_CODE
	Ring configure via SciClient function. More...

#define	ETH_STOP_SEC_CODE

#define	ETH_PRE_COMPILE_VARIANT (STD_ON)
	Eth configuration variant. More...

#define	ETH_LINK_TIME_VARIANT (STD_OFF)

#define	ETH_POST_BUILD_VARIANT (STD_OFF)

#define	ETH_DMA_IR_SUPPORT (STD_ON)
	Eth DMA feature flag support. More...

#define	ETH_DMA_CQ_RING_SUPPORT (STD_ON)

#define	ETH_DMA_TEARDOWN_SUPPORT (STD_ON)

#define	ETH_DMA_PROXY_SUPPORT (STD_ON)

#define	UDMA_DEVICE_ID_RING (235U)
	Eth DMA devices ID. More...

#define	UDMA_DEVICE_ID_UDMA (236U)

#define	UDMA_DEVICE_ID_PSIL (232U)

#define	UDMA_DEVICE_ID_IA (233U)

#define	UDMA_DEVICE_ID_IR (237U)

#define	UDMA_DEVICE_ID_CORE (250U)

#define	UDMA_DEVICE_ID_PROXY (234U)

#define	UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U)
	Eth DMA peer and thread offset. More...

#define	UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U)

#define	UDMA_SOURCE_THREAD_OFFSET (0x6000U)

#define	UDMA_DEST_THREAD_OFFSET (0xe000U)

#define	ETH_DMA_TX_BASE_REG (0x2aa00000U)
	Eth DMA base register address. More...

#define	ETH_DMA_RX_BASE_REG (0x2a800000U)

#define	ETH_DMA_RINGRT_BASE (0x2b800000U)

#define	ETH_DMA_RINGCFG_BASE (0x28440000U)

#define	ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U)

#define	ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U))
	Eth DMA macro to calculate register address for DMA register address. More...

#define	ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U))

#define	ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U))

#define	ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U))

#define	ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U))

#define	ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U))

#define	ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U))

#define	ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U))

#define	ETH_DMA_RINGRT_RING_HWOCC(RING) (0x00000020U + ((RING) * 0x1000U))

#define	ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U))

#define	ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U))

#define	ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U))

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U))

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U))

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U))

#define	Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum)))

#define	Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum)))

#define	Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum)))

#define	Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum)))

#define	Eth_GetRingHWOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum)))

#define	Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum)))

#define	Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId)))

#define	Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId)))

#define	Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId)))

#define	Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId)))

#define	CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U)

#define	CSL_PROXY_TARGET0_PROXY_CTL(PROXY) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U))

#define	CSL_PROXY_TARGET0_PROXY_DATA_FIELD(PROXY) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U))

#define	Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT )
	ETH DEM Error codes to report. More...

#define	Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT )

#define	Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE )
	Eth function like macro to access controler configuration. More...

#define	Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U )

#define	Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0xFFFFU )

#define	Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE )

#define	Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR )

#define	Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR )

#define	Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE )

#define	Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE )

#define	Eth_GetMdioEnableInterrupt(CtrlIndex) ( TRUE )

#define	Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G )

#define	Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 )

#define	Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU )

#define	Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU )

#define	Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE )

#define	Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL )

#define	Eth_GetLoopBackMode(CtrlIndex) ( FALSE )

#define	Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U )

#define	Eth_IsPacketMemCacheable(CtrlIndex) ( TRUE )

#define	Eth_IsRingMemCacheable(CtrlIndex) ( TRUE )

#define	Eth_IsDescMemCacheable(CtrlIndex) ( TRUE )

#define	Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U )

#define	Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U )

#define	Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U )

#define	Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U )

#define	Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U )

#define	Eth_Cpsw_GetCppiClockFreq() ( 333333333U )

#define	Eth_Cpsw_GetCptsRefClockFreq(CtrlIndex) ( 1U )

#define	Eth_Cpsw_GetMdioBusClockFreq(CtrlIndex) ( 2200000U )

#define	Eth_Cpsw_GetMdioOpMode(CtrlIndex) ( ETH_MDIO_OPMODE_MANUAL )

#define	Eth_GetRxMtuLength(CtrlIndex) ( 1522U )

#define	Eth_GetTxChanStartNum(CtrlIndex) ( 30U )

#define	Eth_GetRxChanStartNum(CtrlIndex) ( 30U )

#define	Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U )

#define	Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U )

#define	Eth_GetRingTotalNum(CtrlIndex) ( 6U )

#define	Eth_GetTxChanTotalNum(CtrlIndex) ( 1U )

#define	Eth_GetRxChanTotalNum(CtrlIndex) ( 1U )

#define	Eth_GetFlowTotalNumber(CtrlIndex) ( 1U )

#define	Eth_GetEventTotalNum(CtrlIndex) ( 2U )

#define	Eth_GetRingEventTotalNum(CtrlIndex) ( 2U )

#define	Eth_GetTxDmaThresholdNum(CtrlIndex) ( 1U )

#define	Eth_GetRxDmaThresholdNum(CtrlIndex) ( 1U )

#define	Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U )

#define	Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U )

#define	Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U )

#define	Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U )

#define	Eth_GetEgressFifoPriorityAsignment(CtrlIndex, Prio) ( 0U )

#define	Eth_GetIngressFifoPriorirtyAsignment(CtrlIndex, Prio) ( 0U )

#define	Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] )

#define	Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo )

#define	Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] )

#define	Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 )

#define	Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] )

#define	Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val )

#define	Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] )

#define	Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo )

#define	Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] )

#define	Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 )

#define	Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] )

#define	Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val )

#define	Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U )

#define	Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U )

#define	Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U )

#define	Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U )

#define	Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U )

#define	Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U )

#define	Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U )

#define	Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U )

#define	Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U )

#define	Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U )

#define	Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U )

#define	Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U )

#define	Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U )

#define	Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U )

#define	Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] )

#define	Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId )

#define	Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size )

#define	Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority )

#define	Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr )

#define	Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx )

#define	Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent )

#define	Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum )

#define	Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx )

#define	Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset )

#define	Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )

#define	Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )

#define	Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )

#define	Eth_GetTxEventCoreIntrNum(CtrlIndex) ( 80U )

#define	Eth_GetRxEventCoreIntrNum(CtrlIndex) ( 81U )

#define	Eth_GetHwTimerTotalNum(CtrlIndex) ( 0U )

#define	Eth_GetHwTimerId(CtrlIndex, Index) ( 0xFFU )

#define	Eth_GetHwTimerCounter(CtrlIndex, Index) ( 0xFFU )

#define	Eth_GetHwTimerIntervalMs(CtrlIndex, Index) ( 0xFFFFFFFFU )

#define	Eth_GetHwTimerBaseAddr(CtrlIndex, Index) ( 0xFFFFFFFFU )

#define	Eth_GetHwTimerDynRunningState(CtrlIndex, Index) ( FALSE )

#define	Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val) ( (void)(CtrlIndex) )

#define	Eth_GetRxIrqPacingEnable(CtrlIndex) ( FALSE )

#define	Eth_GetTxIrqPacingEnable(CtrlIndex) ( FALSE )

#define	Eth_GetRxHwTimerIdx(CtrlIndex) ( 255U )

#define	Eth_GetTxHwTimerIdx(CtrlIndex) ( 255U )

#define	Eth_GetIrqPacingEnable(CtrlIndex) ( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) \|\| (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) )

#define	Eth_GetProxyTotalNum(CtrlIndex) ( 1U )

#define	Eth_GetProxyThreadNum(CtrlIndex, ProxyIdx) ( 9U )

#define	Eth_GetProxyTargetRingNum(CtrlIndex, ProxyIdx) ( 0U )

#define	Eth_GetRingProxyIdx(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx )

#define	Eth_GetRingMode(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].ringMode )

#define	Eth_GetDmaRingCfg(CtrlIdx) ( &AppUtils_EthRingCfg )

Macro Definition Documentation

◆ ETH_VERSION_INFO_API

#define ETH_VERSION_INFO_API (STD_ON)

Enable/disable SPI get version info API.

◆ ETH_GLOBALTIMESUPPORT_API

#define ETH_GLOBALTIMESUPPORT_API (STD_ON)

Enable/disable Eth time sync related API.

◆ ETH_DEV_ERROR_DETECT

#define ETH_DEV_ERROR_DETECT (STD_ON)

Enable/disable Development Error Detection.

◆ ETH_GET_COUNTER_VALUES_API

#define ETH_GET_COUNTER_VALUES_API (STD_ON)

Enable/disable Eth get counter values API.

◆ ETH_GET_RX_STATS_API

#define ETH_GET_RX_STATS_API (STD_ON)

Enable/disable Eth get RX stats count API.

◆ ETH_GET_TX_STATS_API

#define ETH_GET_TX_STATS_API (STD_ON)

Enable/disable Eth get TX stats count API.

◆ ETH_GET_TX_ERROR_COUNTERSVALUES_API

#define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON)

Enable/disable Eth get TX error stats count API.

◆ ETH_ZERO_COPY_API

#define ETH_ZERO_COPY_API (STD_OFF)

Enable/disable Eth Zero-Copy support related APIs.

◆ ETH_HEADER_ACCESS_API

#define ETH_HEADER_ACCESS_API (STD_OFF)

Enable/disable Eth Tx/Rx Header Access related APIs.

◆ ETH_TRAFFIC_SHAPING_API

#define ETH_TRAFFIC_SHAPING_API (STD_OFF)

Enable/disable Eth Traffic Shaping related APIs.

◆ ETH_GET_COUNTER_STATE_API

#define ETH_GET_COUNTER_STATE_API (STD_OFF)

Enable/disable Eth get Counter state API.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF)

Enable/disable Hardware Offloading for ICMP checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF)

Enable/disable Hardware offloading for IPv4 Header checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF)

Enable/disable Hardware offloading for TCP checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF)

Enable/disable Hardware offloading for UDP checksums.

◆ ETH_ENABLE_MII_API

#define ETH_ENABLE_MII_API (STD_ON)

Enable/disable Eth MII related API.

◆ ETH_UPDATE_PHYS_ADDR_FILTER_API

#define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON)

Enable/disable optional API Eth_UpdatePhysAddrFilter.

◆ ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API

#define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF)

Enable/disable optional API Eth_NotifyVirtmacMsgReceived.

◆ ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API

#define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic.

◆ ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API

#define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic.

◆ ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API

#define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac.

◆ ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API

#define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac.

◆ ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API

#define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr.

◆ ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API

#define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr.

◆ ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API

#define ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr.

◆ ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API

#define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr.

◆ ETH_VIRTUALMAC_DEL_MACADDR_API

#define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDelAddr.

◆ ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API

#define ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF)

Enable/disable optional API Eth_SendCustomNotify.

◆ ETH_VIRTUALMAC_ADD_VLAN_API

#define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAddVlan.

◆ ETH_VIRTUALMAC_DEL_VLAN_API

#define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDelVlan.

◆ ETH_ETHIF_CBK_HEADER

#define ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h"

EthIf Callback Header File to include inside the Eth driver.

◆ ETH_ISR_TYPE

#define ETH_ISR_TYPE (ETH_ISR_CAT2)

ISR type.

◆ ETH_OS_COUNTER_ID

#define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0)

Counter ID for counter used to count wait ticks.

◆ ETH_OS_COUNTER_FREQ

#define ETH_OS_COUNTER_FREQ (1000000000U)

Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID.

◆ ETH_INVALID_RING_ID

#define ETH_INVALID_RING_ID (0xFFFFU)

Eth Invalid Ring Id value.

◆ ETH_INVALID_EVENT_ID

#define ETH_INVALID_EVENT_ID (0xFFFFU)

Eth Invalid Event Id value.

◆ ETH_INVALID_CHAN_ID

#define ETH_INVALID_CHAN_ID (0xFFFFU)

Eth Invalid channel Id.

◆ ETH_INVALID_FLOW_ID

#define ETH_INVALID_FLOW_ID (0xFFFFU)

Eth Invalid Flow Id.

◆ ETH_INVALID_IRQ_ID

#define ETH_INVALID_IRQ_ID (0xFFFFU)

Eth Invalid IRQ value.

◆ ETH_DEM_NO_EVENT

#define ETH_DEM_NO_EVENT (0xFFFFU)

Eth invalid DEM event ID.

◆ ETH_VIRTUALMAC_SUPPORT

#define ETH_VIRTUALMAC_SUPPORT (STD_OFF)

Enable/disable Virtual MAC support.

◆ ETH_VIRTUALMAC_FWINFO_TIMEOUT

#define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U)

Timeout value for Firmware Attach msg received from server.

◆ EthConf_EthCtrlConfig_EthConfig_0

#define EthConf_EthCtrlConfig_EthConfig_0 (0U)

Eth controller ID Configured controller ID(s)

Controller config

◆ ETH_PRE_COMPILE_VARIANT

#define ETH_PRE_COMPILE_VARIANT (STD_ON)

Eth configuration variant.

◆ ETH_LINK_TIME_VARIANT

#define ETH_LINK_TIME_VARIANT (STD_OFF)

◆ ETH_POST_BUILD_VARIANT

#define ETH_POST_BUILD_VARIANT (STD_OFF)

◆ ETH_CTRL_ID_MAX

#define ETH_CTRL_ID_MAX (1u)

Eth max controller ID.

◆ ETH_DMA_IR_SUPPORT

#define ETH_DMA_IR_SUPPORT (STD_ON)

Eth DMA feature flag support.

◆ ETH_DMA_CQ_RING_SUPPORT

#define ETH_DMA_CQ_RING_SUPPORT (STD_ON)

◆ ETH_DMA_TEARDOWN_SUPPORT

#define ETH_DMA_TEARDOWN_SUPPORT (STD_ON)

◆ ETH_DMA_PROXY_SUPPORT

#define ETH_DMA_PROXY_SUPPORT (STD_ON)

◆ UDMA_DEVICE_ID_RING

#define UDMA_DEVICE_ID_RING (235U)

Eth DMA devices ID.

◆ UDMA_DEVICE_ID_UDMA

#define UDMA_DEVICE_ID_UDMA (236U)

◆ UDMA_DEVICE_ID_PSIL

#define UDMA_DEVICE_ID_PSIL (232U)

◆ UDMA_DEVICE_ID_IA

#define UDMA_DEVICE_ID_IA (233U)

◆ UDMA_DEVICE_ID_IR

#define UDMA_DEVICE_ID_IR (237U)

◆ UDMA_DEVICE_ID_CORE

#define UDMA_DEVICE_ID_CORE (250U)

◆ UDMA_DEVICE_ID_PROXY

#define UDMA_DEVICE_ID_PROXY (234U)

◆ UDMA_TX_CHANNEL_PEER_OFFSET

#define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U)

Eth DMA peer and thread offset.

◆ UDMA_RX_CHANNEL_PEER_OFFSET

#define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U)

◆ UDMA_SOURCE_THREAD_OFFSET

#define UDMA_SOURCE_THREAD_OFFSET (0x6000U)

◆ UDMA_DEST_THREAD_OFFSET

#define UDMA_DEST_THREAD_OFFSET (0xe000U)

◆ ETH_DMA_TX_BASE_REG

#define ETH_DMA_TX_BASE_REG (0x2aa00000U)

Eth DMA base register address.

◆ ETH_DMA_RX_BASE_REG

#define ETH_DMA_RX_BASE_REG (0x2a800000U)

◆ ETH_DMA_RINGRT_BASE

#define ETH_DMA_RINGRT_BASE (0x2b800000U)

◆ ETH_DMA_RINGCFG_BASE

#define ETH_DMA_RINGCFG_BASE (0x28440000U)

◆ ETH_DMA_INTAGGR_INTR_BASE

#define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U)

◆ ETH_DMA_TXCRT_CHAN_CTL

#define ETH_DMA_TXCRT_CHAN_CTL ( CHAN ) (0x00000000U + ((CHAN) * 0x1000U))

Eth DMA macro to calculate register address for DMA register address.

◆ ETH_DMA_TXCRT_CHAN_PEER8

#define ETH_DMA_TXCRT_CHAN_PEER8 ( CHAN ) (0x00000220U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RXCRT_CHAN_CTL

#define ETH_DMA_RXCRT_CHAN_CTL ( CHAN ) (0x00000000U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RXCRT_CHAN_PEER8

#define ETH_DMA_RXCRT_CHAN_PEER8 ( CHAN ) (0x00000220U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_FDB

#define ETH_DMA_RINGRT_RING_FDB ( RING ) (0x00000010U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_FOCC

#define ETH_DMA_RINGRT_RING_FOCC ( RING ) (0x00000018U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_RDB

#define ETH_DMA_RINGRT_RING_RDB ( RING ) (0x00000010U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_ROCC

#define ETH_DMA_RINGRT_RING_ROCC ( RING ) (0x00000018U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_HWOCC

#define ETH_DMA_RINGRT_RING_HWOCC ( RING ) (0x00000020U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGCFG_RING_SIZE

#define ETH_DMA_RINGCFG_RING_SIZE ( RING ) (0x00000048U + ((RING) * 0x100U))

◆ ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET

#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET ( VINT ) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR

#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR ( VINT ) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET

#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET ( VINT ) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR

#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR ( VINT ) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUSM

#define ETH_DMA_INTAGGR_INTR_VINT_STATUSM ( VINT ) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U))

◆ Eth_GetRingFDBReg

#define Eth_GetRingFDBReg ( RingNum ) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum)))

◆ Eth_GetRingFOCCReg

#define Eth_GetRingFOCCReg ( RingNum ) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum)))

◆ Eth_GetRingRDBReg

#define Eth_GetRingRDBReg ( RingNum ) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum)))

◆ Eth_GetRingROCCReg

#define Eth_GetRingROCCReg ( RingNum ) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum)))

◆ Eth_GetRingHWOCCReg

#define Eth_GetRingHWOCCReg ( RingNum ) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum)))

◆ Eth_GetRingSizeReg

#define Eth_GetRingSizeReg ( RingNum ) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum)))

◆ Eth_GetTxChannelCtlRegAddress

#define Eth_GetTxChannelCtlRegAddress ( ChanId ) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId)))

◆ Eth_GetTxChannelPeer8RegAddress

#define Eth_GetTxChannelPeer8RegAddress ( ChanId ) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId)))

◆ Eth_GetRxChannelCtlRegAddress

#define Eth_GetRxChannelCtlRegAddress ( ChanId ) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId)))

◆ Eth_GetRxChannelPeer8RegAddress

#define Eth_GetRxChannelPeer8RegAddress ( ChanId ) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId)))

◆ CSL_PROXY0_TARGET0_DATA_BASE

#define CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U)

◆ CSL_PROXY_TARGET0_PROXY_CTL

#define CSL_PROXY_TARGET0_PROXY_CTL ( PROXY ) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U))

◆ CSL_PROXY_TARGET0_PROXY_DATA_FIELD

#define CSL_PROXY_TARGET0_PROXY_DATA_FIELD ( PROXY ) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U))

◆ UDMA_WAIT_TEARDOWN_COUNTER

#define UDMA_WAIT_TEARDOWN_COUNTER (10000u)

Eth DMA max teardown timeout.

◆ Eth_GetDem_E_HARDWARE_ERROR

#define Eth_GetDem_E_HARDWARE_ERROR ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

ETH DEM Error codes to report.

◆ Eth_GetDem_E_LATECOLLISION

#define Eth_GetDem_E_LATECOLLISION ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_MULTIPLECOLLISION

#define Eth_GetDem_E_MULTIPLECOLLISION ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_SINGLECOLLISION

#define Eth_GetDem_E_SINGLECOLLISION ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_ALIGNMENT

#define Eth_GetDem_E_ALIGNMENT ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_OVERSIZEFRAME

#define Eth_GetDem_E_OVERSIZEFRAME ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_UNDERSIZEFRAME

#define Eth_GetDem_E_UNDERSIZEFRAME ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_CRC

#define Eth_GetDem_E_CRC ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_RX_FRAMES_LOST

#define Eth_GetDem_E_RX_FRAMES_LOST ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_ACCESS

#define Eth_GetDem_E_ACCESS ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_TX_INTERNAL

#define Eth_GetDem_E_TX_INTERNAL ( CtrlIndex ) ( ETH_DEM_NO_EVENT )

◆ Eth_IsVirtualMacModeEnable

#define Eth_IsVirtualMacModeEnable ( CtrlIndex ) ( FALSE )

Eth function like macro to access controler configuration.

◆ Eth_GetTxChannelThreadOffset

#define Eth_GetTxChannelThreadOffset ( CtrlIndex ) ( 0xf000U )

◆ Eth_VirtMacGetEthFwRpcComChannelId

#define Eth_VirtMacGetEthFwRpcComChannelId ( CtrlIndex ) ( 0xFFFFU )

◆ Eth_VirtMacGetEthPollRecvMsgInEthMain

#define Eth_VirtMacGetEthPollRecvMsgInEthMain ( CtrlIndex ) ( FALSE )

◆ Eth_VirtMacGetRpcCmdCompleteFuncPtr

#define Eth_VirtMacGetRpcCmdCompleteFuncPtr ( CtrlIndex ) ( (Eth_RpcCmdComplete)NULL_PTR )

◆ Eth_VirtMacGetFwRegisterFuncPtr

#define Eth_VirtMacGetFwRegisterFuncPtr ( CtrlIndex ) ( (Eth_RpcFwRegistered)NULL_PTR )

◆ Eth_GetTxEnableInterrupt

#define Eth_GetTxEnableInterrupt ( CtrlIndex ) ( TRUE )

◆ Eth_GetRxEnableInterrupt

#define Eth_GetRxEnableInterrupt ( CtrlIndex ) ( TRUE )

◆ Eth_GetMdioEnableInterrupt

#define Eth_GetMdioEnableInterrupt ( CtrlIndex ) ( TRUE )

◆ Eth_GetEnetType

#define Eth_GetEnetType ( CtrlIndex ) ( ETH_ENETTYPE_CPSW2G )

◆ Eth_GetMacPortNum

#define Eth_GetMacPortNum ( CtrlIndex ) ( ETH_PORT_MAC_PORT_1 )

◆ Eth_GetMacAddressHigh

#define Eth_GetMacAddressHigh ( CtrlIndex ) ( 0xaabbccddU )

◆ Eth_GetMacAddressLow

#define Eth_GetMacAddressLow ( CtrlIndex ) ( 0xeeffU )

◆ Eth_UseDefaultMacAddress

#define Eth_UseDefaultMacAddress ( CtrlIndex ) ( TRUE )

◆ Eth_GetMiiConnectionType

#define Eth_GetMiiConnectionType ( CtrlIndex ) ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL )

◆ Eth_GetLoopBackMode

#define Eth_GetLoopBackMode ( CtrlIndex ) ( FALSE )

◆ Eth_GetHardwareLoopTimeout

#define Eth_GetHardwareLoopTimeout ( CtrlIndex ) ( 32000U )

◆ Eth_IsPacketMemCacheable

#define Eth_IsPacketMemCacheable ( CtrlIndex ) ( TRUE )

◆ Eth_IsRingMemCacheable

#define Eth_IsRingMemCacheable ( CtrlIndex ) ( TRUE )

◆ Eth_IsDescMemCacheable

#define Eth_IsDescMemCacheable ( CtrlIndex ) ( TRUE )

◆ Eth_Cpsw_GetPhyMacRegAddr

#define Eth_Cpsw_GetPhyMacRegAddr ( ) ( 0x40f00200U )

◆ Eth_Cpsw_GetAleRegAddr

#define Eth_Cpsw_GetAleRegAddr ( ) ( 0x4603e000U )

◆ Eth_Cpsw_GetCptsRegAddr

#define Eth_Cpsw_GetCptsRegAddr ( ) ( 0x4603d000U )

◆ Eth_Cpsw_GetMdioRegAddr

#define Eth_Cpsw_GetMdioRegAddr ( ) ( 0x46000f00U )

◆ Eth_Cpsw_GetCtrlRegAddr

#define Eth_Cpsw_GetCtrlRegAddr ( ) ( 0x46020000U )

◆ Eth_Cpsw_GetCppiClockFreq

#define Eth_Cpsw_GetCppiClockFreq ( ) ( 333333333U )

◆ Eth_Cpsw_GetCptsRefClockFreq

#define Eth_Cpsw_GetCptsRefClockFreq ( CtrlIndex ) ( 1U )

◆ Eth_Cpsw_GetMdioBusClockFreq

#define Eth_Cpsw_GetMdioBusClockFreq ( CtrlIndex ) ( 2200000U )

◆ Eth_Cpsw_GetMdioOpMode

#define Eth_Cpsw_GetMdioOpMode ( CtrlIndex ) ( ETH_MDIO_OPMODE_MANUAL )

◆ Eth_GetRxMtuLength

#define Eth_GetRxMtuLength ( CtrlIndex ) ( 1522U )

◆ Eth_GetTxChanStartNum

#define Eth_GetTxChanStartNum ( CtrlIndex ) ( 30U )

◆ Eth_GetRxChanStartNum

#define Eth_GetRxChanStartNum ( CtrlIndex ) ( 30U )

◆ Eth_GetEgressFifoTotalNum

#define Eth_GetEgressFifoTotalNum ( CtrlIndex ) ( 1U )

◆ Eth_GetIngressFifoTotalNum

#define Eth_GetIngressFifoTotalNum ( CtrlIndex ) ( 1U )

◆ Eth_GetRingTotalNum

#define Eth_GetRingTotalNum ( CtrlIndex ) ( 6U )

◆ Eth_GetTxChanTotalNum

#define Eth_GetTxChanTotalNum ( CtrlIndex ) ( 1U )

◆ Eth_GetRxChanTotalNum

#define Eth_GetRxChanTotalNum ( CtrlIndex ) ( 1U )

◆ Eth_GetFlowTotalNumber

#define Eth_GetFlowTotalNumber ( CtrlIndex ) ( 1U )

◆ Eth_GetEventTotalNum

#define Eth_GetEventTotalNum ( CtrlIndex ) ( 2U )

◆ Eth_GetRingEventTotalNum

#define Eth_GetRingEventTotalNum ( CtrlIndex ) ( 2U )

◆ Eth_GetTxDmaThresholdNum

#define Eth_GetTxDmaThresholdNum ( CtrlIndex ) ( 1U )

◆ Eth_GetRxDmaThresholdNum

#define Eth_GetRxDmaThresholdNum ( CtrlIndex ) ( 1U )

◆ Eth_GetEgressFifoPacketNum

#define Eth_GetEgressFifoPacketNum	(	CtrlIndex,
		FifoIdx
	)	( 16U )

◆ Eth_GetEgressFifoPacketSize

#define Eth_GetEgressFifoPacketSize	(	CtrlIndex,
		FifoIdx
	)	( 1522U )

◆ Eth_GetIngressFifoPacketNum

#define Eth_GetIngressFifoPacketNum	(	CtrlIndex,
		FifoIdx
	)	( 16U )

◆ Eth_GetIngressFifoPacketSize

#define Eth_GetIngressFifoPacketSize	(	CtrlIndex,
		FifoIdx
	)	( 1522U )

◆ Eth_GetEgressFifoPriorityAsignment

#define Eth_GetEgressFifoPriorityAsignment	(	CtrlIndex,
		Prio
	)	( 0U )

◆ Eth_GetIngressFifoPriorirtyAsignment

#define Eth_GetIngressFifoPriorirtyAsignment	(	CtrlIndex,
		Prio
	)	( 0U )

◆ Eth_GetEgressFifoDescAddress

#define Eth_GetEgressFifoDescAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] )

◆ Eth_GetEgressFifoDescUserInfoAddress

#define Eth_GetEgressFifoDescUserInfoAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo )

◆ Eth_GetEgressFifoBufferDataAddress

#define Eth_GetEgressFifoBufferDataAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] )

◆ Eth_GetEgressFifoQueueAddress

#define Eth_GetEgressFifoQueueAddress	(	CtrlIndex,
		FifoIdx
	)	( Eth_Ctrl_0_Egress_Queue_0 )

◆ Eth_GetEgressFifoBufferState

#define Eth_GetEgressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx
	)	( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] )

◆ Eth_SetEgressFifoBufferState

#define Eth_SetEgressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx,
		Val
	)	( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val )

◆ Eth_GetIngressFifoDescAddress

#define Eth_GetIngressFifoDescAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] )

◆ Eth_GetIngressFifoDescUserInfoAddress

#define Eth_GetIngressFifoDescUserInfoAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo )

◆ Eth_GetIngressFifoBufferDataAddress

#define Eth_GetIngressFifoBufferDataAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx
	)	(&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] )

◆ Eth_GetIngressFifoQueueAddress

#define Eth_GetIngressFifoQueueAddress	(	CtrlIndex,
		FifoIdx
	)	( Eth_Ctrl_0_Ingress_Queue_0 )

◆ Eth_GetIngressFifoBufferState

#define Eth_GetIngressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx
	)	( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] )

◆ Eth_SetIngressFifoBufferState

#define Eth_SetIngressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx,
		Val
	)	( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val )

◆ Eth_GetEgressFifoCqIdx

#define Eth_GetEgressFifoCqIdx	(	CtrlIndex,
		FifoIdx
	)	( 0U )

◆ Eth_GetEgressFifoFqIdx

#define Eth_GetEgressFifoFqIdx	(	CtrlIndex,
		FifoIdx
	)	( 2U )

◆ Eth_GetIngressFifoCqIdx

#define Eth_GetIngressFifoCqIdx	(	CtrlIndex,
		FifoIdx
	)	( 1U )

◆ Eth_GetIngressFifoFqIdx

#define Eth_GetIngressFifoFqIdx	(	CtrlIndex,
		FifoIdx
	)	( 3U )

◆ Eth_GetTxChanId

#define Eth_GetTxChanId	(	CtrlIndex,
		ChIdx
	)	( 30U )

◆ Eth_GetTxChanTdCqRingIdx

#define Eth_GetTxChanTdCqRingIdx	(	CtrlIndex,
		ChIdx
	)	( 4U )

◆ Eth_GetTxChanDepth

#define Eth_GetTxChanDepth	(	CtrlIndex,
		ChIdx
	)	( 128U )

◆ Eth_GetRxChanId

#define Eth_GetRxChanId	(	CtrlIndex,
		ChIdx
	)	( 30U )

◆ Eth_GetRxChanTdCqRingIdx

#define Eth_GetRxChanTdCqRingIdx	(	CtrlIndex,
		ChIdx
	)	( 5U )

◆ Eth_GetRxChanFlowTotalNum

#define Eth_GetRxChanFlowTotalNum	(	CtrlIndex,
		ChIdx
	)	( 1U )

◆ Eth_GetRxChanFlowStartNum

#define Eth_GetRxChanFlowStartNum	(	CtrlIndex,
		ChIdx
	)	( 60U )

◆ Eth_GetFlowId

#define Eth_GetFlowId	(	CtrlIndex,
		FlowIdx
	)	( 60U )

◆ Eth_GetFlowCqRingIdx

#define Eth_GetFlowCqRingIdx	(	CtrlIndex,
		FlowIdx
	)	( 1U )

◆ Eth_GetFlowFqRingIdx

#define Eth_GetFlowFqRingIdx	(	CtrlIndex,
		FlowIdx
	)	( 3U )

◆ Eth_GetDynRingElemAddress

#define Eth_GetDynRingElemAddress	(	CtrlIndex,
		RingIdx
	)	( &Eth_RingDyn_Ctrl_0[(RingIdx)] )

◆ Eth_GetRingHwId

#define Eth_GetRingHwId	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].hwId )

◆ Eth_GetRingTotalElemNum

#define Eth_GetRingTotalElemNum	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].size )

◆ Eth_GetRingPriority

#define Eth_GetRingPriority	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].priority )

◆ Eth_GetRingMemBaseAddress

#define Eth_GetRingMemBaseAddress	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].memPtr )

◆ Eth_GetRingEventRingIdx

#define Eth_GetRingEventRingIdx	(	CtrlIndex,
		RingEvtIdx
	)	( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx )

◆ Eth_GetRingEventGlobalEventNum

#define Eth_GetRingEventGlobalEventNum	(	CtrlIndex,
		RingEvtIdx
	)	( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent )

◆ Eth_GetRingEventVirtBitNum

#define Eth_GetRingEventVirtBitNum	(	CtrlIndex,
		RingEvtIdx
	)	( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum )

◆ Eth_GetRingEventEventIdx

#define Eth_GetRingEventEventIdx	(	CtrlIndex,
		RingEvtIdx
	)	( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx )

◆ Eth_GetRingEventSrcOffsetNum

#define Eth_GetRingEventSrcOffsetNum	(	CtrlIndex,
		RingEvtIdx
	)	( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset )

◆ Eth_GetEventCoreIntrNum

#define Eth_GetEventCoreIntrNum	(	CtrlIndex,
		EvtIdx
	)	( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )

◆ Eth_GetEventVirtIntrNum

#define Eth_GetEventVirtIntrNum	(	CtrlIndex,
		EvtIdx
	)	( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )

◆ Eth_GetEventIrIntrNum

#define Eth_GetEventIrIntrNum	(	CtrlIndex,
		EvtIdx
	)	( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )

◆ Eth_GetTxEventCoreIntrNum

#define Eth_GetTxEventCoreIntrNum ( CtrlIndex ) ( 80U )

◆ Eth_GetRxEventCoreIntrNum

#define Eth_GetRxEventCoreIntrNum ( CtrlIndex ) ( 81U )

◆ Eth_GetHwTimerTotalNum

#define Eth_GetHwTimerTotalNum ( CtrlIndex ) ( 0U )

◆ Eth_GetHwTimerId

#define Eth_GetHwTimerId	(	CtrlIndex,
		Index
	)	( 0xFFU )

◆ Eth_GetHwTimerCounter

#define Eth_GetHwTimerCounter	(	CtrlIndex,
		Index
	)	( 0xFFU )

◆ Eth_GetHwTimerIntervalMs

#define Eth_GetHwTimerIntervalMs	(	CtrlIndex,
		Index
	)	( 0xFFFFFFFFU )

◆ Eth_GetHwTimerBaseAddr

#define Eth_GetHwTimerBaseAddr	(	CtrlIndex,
		Index
	)	( 0xFFFFFFFFU )

◆ Eth_GetHwTimerDynRunningState

#define Eth_GetHwTimerDynRunningState	(	CtrlIndex,
		Index
	)	( FALSE )

◆ Eth_SetHwTimerDynRunningState

#define Eth_SetHwTimerDynRunningState	(	CtrlIndex,
		Index,
		Val
	)	( (void)(CtrlIndex) )

◆ Eth_GetRxIrqPacingEnable

#define Eth_GetRxIrqPacingEnable ( CtrlIndex ) ( FALSE )

◆ Eth_GetTxIrqPacingEnable

#define Eth_GetTxIrqPacingEnable ( CtrlIndex ) ( FALSE )

◆ Eth_GetRxHwTimerIdx

#define Eth_GetRxHwTimerIdx ( CtrlIndex ) ( 255U )

◆ Eth_GetTxHwTimerIdx

#define Eth_GetTxHwTimerIdx ( CtrlIndex ) ( 255U )

◆ Eth_GetIrqPacingEnable

#define Eth_GetIrqPacingEnable ( CtrlIndex ) ( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) || (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) )

◆ Eth_GetProxyTotalNum

#define Eth_GetProxyTotalNum ( CtrlIndex ) ( 1U )

◆ Eth_GetProxyThreadNum

#define Eth_GetProxyThreadNum	(	CtrlIndex,
		ProxyIdx
	)	( 9U )

◆ Eth_GetProxyTargetRingNum

#define Eth_GetProxyTargetRingNum	(	CtrlIndex,
		ProxyIdx
	)	( 0U )

◆ Eth_GetRingProxyIdx

#define Eth_GetRingProxyIdx	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx )

◆ Eth_GetRingMode

#define Eth_GetRingMode	(	CtrlIndex,
		RingIdx
	)	( Eth_Udma_RingCfg_0[(RingIdx)].ringMode )

◆ Eth_GetDmaRingCfg

#define Eth_GetDmaRingCfg ( CtrlIdx ) ( &AppUtils_EthRingCfg )

◆ ETH_START_SEC_CONST_UNSPECIFIED

#define ETH_START_SEC_CONST_UNSPECIFIED

◆ ETH_STOP_SEC_CONST_UNSPECIFIED

#define ETH_STOP_SEC_CONST_UNSPECIFIED

◆ ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

◆ ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

◆ ETH_START_SEC_VAR_NO_INIT_8

#define ETH_START_SEC_VAR_NO_INIT_8

◆ ETH_STOP_SEC_VAR_NO_INIT_8

#define ETH_STOP_SEC_VAR_NO_INIT_8

◆ ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

◆ ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

◆ ETH_START_SEC_CODE

#define ETH_START_SEC_CODE

Ring configure via SciClient function.

◆ ETH_STOP_SEC_CODE

#define ETH_STOP_SEC_CODE

Typedef Documentation

◆ Eth_RpcCmdComplete

typedef void(* Eth_RpcCmdComplete) (uint8 CtrlIdx, uint8 sid, sint32 status)

Application callback to indicate Rpc dispatch command completion.

Pointer to a function that is invoked to indicate completion of RPC dispatch call. The RPC command is identified by the sid

◆ Eth_RpcFwRegistered

typedef void(* Eth_RpcFwRegistered) (uint8 CtrlIdx)

Application callback to indicate Ethernet firmware registered with the Eth RPC client.

Ring DMA configure function pointer

◆ Eth_DmaRingCfg

typedef Std_ReturnType(* Eth_DmaRingCfg) (uint8 ctrlIdx, uint8 ringIdx)

Enumeration Type Documentation

◆ Eth_PortType

enum Eth_PortType

Port identifier.

Depending on the CPSW Type (for example CPSW9G) multiple ports are supported. The specific port is identified using this enum

Enumerator
ETH_PORT_HOST_PORT	Host port
ETH_MAC_PORT_FIRST	First Eth port
ETH_PORT_MAC_PORT_1	MAC port 0
ETH_PORT_MAC_PORT_2	MAC port 1
ETH_PORT_MAC_PORT_3	MAC port 2
ETH_PORT_MAC_PORT_4	MAC port 3
ETH_PORT_MAC_PORT_5	MAC port 4
ETH_PORT_MAC_PORT_6	MAC port 5
ETH_PORT_MAC_PORT_7	MAC port 6
ETH_PORT_MAC_PORT_8	MAC port 7
ETH_PORT_MAC_PORT_LAST	Enum indicating last mac port

◆ Eth_MacConnectionType

enum Eth_MacConnectionType

Type/Speed/Duplex connection type.

Ethernet connections based on the type (MII, RMII, RGMII), speed (10Mbps, 100Mbps, 1Gbps) and duplexity (half, full).

Enumerator
ETH_MAC_CONN_TYPE_RMII_10	MAC connection type for 10Mbps RMII mode
ETH_MAC_CONN_TYPE_RMII_100	MAC connection type for 100Mbps RMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF	MAC connection type for forced half-duplex 100Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL	MAC connection type for forced full-duplex 100Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL	MAC connection type for forced full-duplex 1000Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND	MAC connection type for RGMII inband detection mode (speed determined based on received RGMII Rx clock)

◆ Eth_EnetType

enum Eth_EnetType

Enet Cpsw Type identifier.

Enet CPSW Type enumeration.

Enumerator
ETH_ENETTYPE_CPSW2G	CPSW 2-port switch with one host port and 1 external port
ETH_ENETTYPE_CPSW9G	CPSW 9-port switch with one host port and 8 external port
ETH_ENETTYPE_CPSW5G	CPSW 5-port switch with one host port and 4 external port
ETH_ENETTYPE_CPSW3G	CPSW 3-port switch with one host port and 2 external port
ETH_ENETTYPE_CPSWLAST	Enum used to identify the last supported CPSW Type. Used internally

◆ Eth_MdioOperModeType

enum Eth_MdioOperModeType

MDIO operating mode.

MDIO operating mode enumeration.

Enumerator
ETH_MDIO_OPMODE_NORMAL	Normal mode
ETH_MDIO_OPMODE_MANUAL	Manual mode (Used for software-emulated MDIO operations)

Function Documentation

◆ VAR() [1/5]

VAR	(	uint8	,
		ETH_VAR_NO_INIT_128
	)

◆ VAR() [2/5]

VAR	(	Eth_DescType	,
		ETH_VAR_NO_INIT_128
	)

◆ VAR() [3/5]

VAR	(	uint8	,
		ETH_VAR_NO_INIT
	)

◆ VAR() [4/5]

VAR	(	Eth_QueueType	,
		ETH_VAR_NO_INIT
	)

◆ VAR() [5/5]

VAR	(	Eth_Udma_RingDynType	,
		ETH_VAR_NO_INIT
	)

◆ AppUtils_EthRingCfg()

Std_ReturnType AppUtils_EthRingCfg	(	uint8	ctrlIdx,
		uint8	Id
	)

Variable Documentation

◆ Eth_Udma_RingCfg_0

const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]

◆ Eth_EventCfg_Ctrl_0

const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]

◆ Eth_RingEventCfg_Ctrl_0

const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]