![]() |
PDK API Guide for J721E
|
Cache Handling routines for the RTOS Porting Interface.
============================================================================
Go to the source code of this file.
Cache coherent type definitions | |
#define | OSAL_CACHEP_COHERENT ((uint32_t) 0U) |
#define | OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U) |
typedef uint32_t | Osal_CacheP_isCoherent |
This enumerator defines the cache coherent types. More... | |
Set Cache MAR register | |
#define | CacheP_Mar_DISABLE (0U) |
#define | CacheP_Mar_ENABLE (1U) |
typedef uint32_t | CacheP_Mar |
This enumerator defines the MAR register setting types. More... | |
Functions | |
void | CacheP_wb (const void *addr, uint32_t size) |
Function to write back cache lines. More... | |
void | CacheP_Inv (const void *addr, uint32_t size) |
Function to invalidate cache lines. More... | |
void | CacheP_wbInv (const void *addr, uint32_t size) |
Function to write back and invalidate cache lines. More... | |
void | CacheP_fenceCpu2Dma (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent) |
Function to call before handing over the memory buffer to DMA from CPU. More... | |
void | CacheP_fenceDma2Cpu (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent) |
Function to call before reading the memory to CPU after DMA operations. More... | |
void | CacheP_setMar (void *baseAddr, uint32_t size, uint32_t value) |
Set MAR attribute for a memory range. More... | |
uint32_t | CacheP_getMar (void *baseAddr) |
Get MAR attribute for a region of 16MB. More... | |