PDK API Guide for J721E
Macros
V1/ipc_soc.h File Reference
IPC Driver
»
IPC SoC Config
Introduction
IPC Low Level Driver J7 SOC specific file.
Go to the source code of this file.
Macros
#define
IPC_VRING_BUFFER_SIZE
(0x1C00000U)
VRing Buffer Size required for all core combinations.
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#define
SUPPORT_C66X_BIT0
#define
IPC_MPU1_0
(0U)
Core definitions.
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#define
IPC_MCU1_0
(1U)
#define
IPC_MCU1_1
(2U)
#define
IPC_MCU2_0
(3U)
#define
IPC_MCU2_1
(4U)
#define
IPC_MAILBOX_CLUSTER_CNT
(12U)
#define
IPC_MAILBOX_USER_CNT
(4U)
#define
MAIN_NAVSS_MAILBOX_INPUTINTR_MAX
(440U)
#define
MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX
(512U)
#define
NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET
(182U)
#define
NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET
(726U)
#define
NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET
(400U)
#define
NAVSS512_MCU1R5F0_INPUT_MAILBOX_VIM_OFFSET
(376U)
#define
NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET
(404U)
#define
NAVSS512_MCU1R5F1_INPUT_MAILBOX_VIM_OFFSET
(380U)
#define
NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET
(216U)
#define
NAVSS512_MCU2R5F0_INPUT_MAILBOX_VIM_OFFSET
(248U)
#define
NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET
(248U)
#define
NAVSS512_MCU2R5F1_INPUT_MAILBOX_VIM_OFFSET
(248U)
#define
NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET
(280U)
#define
NAVSS512_MCU3R5F0_INPUT_MAILBOX_VIM_OFFSET
(248U)
#define
NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET
(312U)
#define
NAVSS512_MCU3R5F1_INPUT_MAILBOX_VIM_OFFSET
(248U)
#define
NAVSS512_C66X1_INPUT_MAILBOX_OFFSET
(344U)
#define
NAVSS512_C66X1_INPUT_MAILBOX_VIM_OFFSET
(97U) /* C66x_intrRouter_0 */
#define
NAVSS512_C66X2_INPUT_MAILBOX_OFFSET
(376U)
#define
NAVSS512_C66X2_INPUT_MAILBOX_VIM_OFFSET
(97U) /* C66x_intrRouter_1 */
#define
NAVSS512_C7X1_INPUT_MAILBOX_OFFSET
(188U)
#define
NAVSS512_C7X1_INPUT_MAILBOX_VIM_OFFSET
(732U)
#define
IPC_MCU_NAVSS0_INTR0_CFG_BASE
(CSL_NAVSS_MAIN_INTR_ROUTER_CFG_REGS_0_BASE)
#define
IPC_C66X_RAT_BASE
(0x07ff0030U)
#define
IPC_C66X_INTR_VA_BASE
(0x18000000U)
#define
IPC_C66X_1_INTR_PA_BASE
(CSL_C66SS0_INTROUTER0_INTR_ROUTER_CFG_BASE)
#define
IPC_C66X_2_INTR_PA_BASE
(CSL_C66SS1_INTROUTER0_INTR_ROUTER_CFG_BASE)
#define
C66X1_MBINTR_INPUT_BASE
(74U)
#define
C66X1_MBINTR_OFFSET
(84U)
#define
C66X1_MBINTR_OUTPUT_BASE
(96U)
#define
C66X2_MBINTR_INPUT_BASE
(74U)
#define
C66X2_MBINTR_OUTPUT_BASE
(96U)
#define
C66X2_MBINTR_OFFSET
(84U)
#define
C7X_CLEC_BASE_ADDR
(CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
#define
C7X_CLEC_OFFSET
(1024U - 32U)
#define
IPC_C7X_MBINTR_OFFSET
(59U)
packages
ti
drv
ipc
soc
V1
ipc_soc.h
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