OSPI Enumerated Data Types

Introduction

OSPI clock mode
This enumerator defines the four possible clock modes, dach mode has different values of clock phase(CKPH) and clock polarity(CKP)
typedef uint32_t	CSL_OspiClkMode
#define	CSL_OSPI_CLK_MODE_0   (0U)
#define	CSL_OSPI_CLK_MODE_1
#define	CSL_OSPI_CLK_MODE_2
#define	CSL_OSPI_CLK_MODE_3

OSPI chip select
This enumerator defines the chip selects available to OSPI. OSPI module have four chip selects to connect to four external devices.
typedef uint32_t	CSL_OspiChipSelect
#define	CSL_OSPI_CS0   ((uint32_t) 0U)
#define	CSL_OSPI_CS1   ((uint32_t) 1U)
#define	CSL_OSPI_CS2   ((uint32_t) 2U)
#define	CSL_OSPI_CS3   ((uint32_t) 3U)

OSPI decoder select
This enumerator defines the decoder select. Chip select 3
typedef uint32_t	CSL_OspiDecSelect
#define	CSL_OSPI_DECODER_SELECT4   ((uint32_t) 0U)
#define	CSL_OSPI_DECODER_SELECT16   ((uint32_t) 1U)

OSPI num of addr bytes in memory mapped mode
This enumerator defines the number of Address bytes to be sent before transfer in memory mapped mode for each chip select
typedef uint32_t	CSL_OspiMemMapNumAddrBytes
#define	CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_1   ((uint32_t) 0U)
#define	CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_2   ((uint32_t) 1U)
#define	CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_3   ((uint32_t) 2U)
#define	CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_4   ((uint32_t) 3U)

PHY operation mode flags
This enumerator defines whether to force half cycle or try achieve full cycle lock.
typedef uint32_t	CSL_OspiPhyOpMode
#define	CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT   ((uint32_t) 0U)
#define	CSL_OSPI_CFG_PHY_OP_MODE_MASTER   ((uint32_t) 1U)
#define	CSL_OSPI_CFG_PHY_OP_MODE_BYPASS   ((uint32_t) 2U)
#define	CSL_OSPI_CFG_PHY_DLL_MODE_DEFAULT   (CSL_OSPI_LOCK_CYCLE_HALF)
#define	CSL_OSPI_LOCK_CYCLE_FULL   ((uint16_t) 0U)
#define	CSL_OSPI_LOCK_CYCLE_HALF   ((uint16_t) 1U)

OSPI number of transfer lines
This enum defines the number of lines controller needs to use.
#define	CSL_OSPI_CFG_XFER_LINES_SINGLE   ((uint32_t) 0U)
#define	CSL_OSPI_CFG_XFER_LINES_DUAL   ((uint32_t) 1U)
#define	CSL_OSPI_CFG_XFER_LINES_QUAD   ((uint32_t) 2U)
#define	CSL_OSPI_CFG_XFER_LINES_OCTAL   ((uint32_t) 3U)

OSPI PHY sample edge select
This enumerator defines whether to sample on rising edge or falling edge
#define	CSL_OSPI_CFG_PHY_SAMPLE_EDGE_DEFAULT   (CSL_OSPI_CFG_PHY_SAMPLE_EDGE_FALLING)
#define	CSL_OSPI_CFG_PHY_SAMPLE_EDGE_FALLING   ((uint16_t) 0U)
#define	CSL_OSPI_CFG_PHY_SAMPLE_EDGE_RISING   ((uint16_t) 1U)

OSPI write completion auto polling state
This enumerator defines the write completion auto polling control states
typedef uint32_t	CSL_OspiWriteCompAutoPolling
#define	CSL_OSPI_WRITE_COMP_AUTO_POLLING_ENABLE   ((uint32_t) 1U)
#define	CSL_OSPI_WRITE_COMP_AUTO_POLLING_DISABLE   ((uint32_t) 0U)

OSPI interrupt mask flags
This enumerator defines the flags of interrupt for OSPI module
typedef uint32_t	CSL_OspiIntrMask
#define	CSL_OSPI_INTR_MASK_MODE_M_FAIL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_MODE_M_FAIL_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_UNDERFLOW_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_UNDERFLOW_DET_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_IND_OP_DONE   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_IND_RD_REJECT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_READ_REJECT_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_PROT_WR_ATTEMPT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_ILLEGAL_ACCESS_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_ILLEGAL_ACCESS_DET_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_RECV_OVERFLOW_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RECV_OVERFLOW_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_TX_FIFO_NOT_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_TX_FIFO_NOT_FULL_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_TX_FIFO_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_TX_FIFO_FULL_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_RX_FIFO_NOT_EMPTY   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RX_FIFO_NOT_EMPTY_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_RX_FIFO_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RX_FIFO_FULL_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_IND_RD_SRAM_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_POLL_EXP_INT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_POLL_EXP_INT_FLD_MASK)
#define	CSL_OSPI_INTR_MASK_IRQ_STAT_RESV   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_IRQ_STAT_RESV_FLD_MASK)

Macro Definition Documentation

CSL_OSPI_CLK_MODE_0

#define CSL_OSPI_CLK_MODE_0   (0U)

Mode 0 - Clock polarity = 0, clock phase = 0

CSL_OSPI_CLK_MODE_1

#define CSL_OSPI_CLK_MODE_1

Value:

(CSL_OSPI_FLASH_CFG_CONFIG_REG_SEL_CLK_PHASE_FLD_MASK | \
                               0U)

Mode 1 - clock polarity = 0, clock phase = 1

CSL_OSPI_CLK_MODE_2

#define CSL_OSPI_CLK_MODE_2

Value:

(0U | \
                               CSL_OSPI_FLASH_CFG_CONFIG_REG_SEL_CLK_POL_FLD_MASK)

Mode 2 - clock polarity = 1, clock phase = 0

CSL_OSPI_CLK_MODE_3

#define CSL_OSPI_CLK_MODE_3

Value:

(CSL_OSPI_FLASH_CFG_CONFIG_REG_SEL_CLK_PHASE_FLD_MASK | \
                               CSL_OSPI_FLASH_CFG_CONFIG_REG_SEL_CLK_POL_FLD_MASK)

Mode 3 - clock polarity = 1, clock phase = 1

CSL_OSPI_CS0

#define CSL_OSPI_CS0   ((uint32_t) 0U)

Chip select 0

CSL_OSPI_CS1

#define CSL_OSPI_CS1   ((uint32_t) 1U)

Chip select 1

CSL_OSPI_CS2

#define CSL_OSPI_CS2   ((uint32_t) 2U)

Chip select 2

CSL_OSPI_CS3

#define CSL_OSPI_CS3   ((uint32_t) 3U)

CSL_OSPI_DECODER_SELECT4

#define CSL_OSPI_DECODER_SELECT4   ((uint32_t) 0U)

1 of 4 decode

CSL_OSPI_DECODER_SELECT16

#define CSL_OSPI_DECODER_SELECT16   ((uint32_t) 1U)

allow external 4 - 16 decode

CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_1

#define CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_1   ((uint32_t) 0U)

One address byte for Chip Select N

CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_2

#define CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_2   ((uint32_t) 1U)

Two address bytes for chip select N

CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_3

#define CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_3   ((uint32_t) 2U)

Three address bytes for chip select N

CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_4

#define CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_4   ((uint32_t) 3U)

Four address bytes for Chip select N

CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT

#define CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT   ((uint32_t) 0U)

Configure PHY operation mode based on OSPI functional clock

CSL_OSPI_CFG_PHY_OP_MODE_MASTER

#define CSL_OSPI_CFG_PHY_OP_MODE_MASTER   ((uint32_t) 1U)

Configure PHY to operate in Master mode

CSL_OSPI_CFG_PHY_OP_MODE_BYPASS

#define CSL_OSPI_CFG_PHY_OP_MODE_BYPASS   ((uint32_t) 2U)

Configure PHY to operate in Bypass mode

CSL_OSPI_CFG_PHY_DLL_MODE_DEFAULT

#define CSL_OSPI_CFG_PHY_DLL_MODE_DEFAULT   (CSL_OSPI_LOCK_CYCLE_HALF)

Configure PHY operation mode based on OSPI functional clock

CSL_OSPI_LOCK_CYCLE_FULL

#define CSL_OSPI_LOCK_CYCLE_FULL   ((uint16_t) 0U)

Configure PHY to operate in Master mode

CSL_OSPI_LOCK_CYCLE_HALF

#define CSL_OSPI_LOCK_CYCLE_HALF   ((uint16_t) 1U)

Configure PHY to operate in Bypass mode

CSL_OSPI_CFG_XFER_LINES_SINGLE

#define CSL_OSPI_CFG_XFER_LINES_SINGLE   ((uint32_t) 0U)

Configure OSPI Controller to use IN:DQ0 OUT:DQ1

CSL_OSPI_CFG_XFER_LINES_DUAL

#define CSL_OSPI_CFG_XFER_LINES_DUAL   ((uint32_t) 1U)

Configure OSPI Controller to use IN:DQ[0:1] OUT:DQ[0:1]

CSL_OSPI_CFG_XFER_LINES_QUAD

#define CSL_OSPI_CFG_XFER_LINES_QUAD   ((uint32_t) 2U)

Configure OSPI Controller to use IN:DQ[0:3] OUT:DQ[0:3]

CSL_OSPI_CFG_XFER_LINES_OCTAL

#define CSL_OSPI_CFG_XFER_LINES_OCTAL   ((uint32_t) 3U)

Configure OSPI Controller to use IN:DQ[0:7] OUT:DQ[0:7]

CSL_OSPI_CFG_PHY_SAMPLE_EDGE_DEFAULT

#define CSL_OSPI_CFG_PHY_SAMPLE_EDGE_DEFAULT   (CSL_OSPI_CFG_PHY_SAMPLE_EDGE_FALLING)

Configure PHY sample edge default

CSL_OSPI_CFG_PHY_SAMPLE_EDGE_FALLING

#define CSL_OSPI_CFG_PHY_SAMPLE_EDGE_FALLING   ((uint16_t) 0U)

Configure PHY to sample on falling edge

CSL_OSPI_CFG_PHY_SAMPLE_EDGE_RISING

#define CSL_OSPI_CFG_PHY_SAMPLE_EDGE_RISING   ((uint16_t) 1U)

Configure PHY to sample on rising edge

CSL_OSPI_WRITE_COMP_AUTO_POLLING_ENABLE

#define CSL_OSPI_WRITE_COMP_AUTO_POLLING_ENABLE   ((uint32_t) 1U)

Write completion auto polling state enable

CSL_OSPI_WRITE_COMP_AUTO_POLLING_DISABLE

#define CSL_OSPI_WRITE_COMP_AUTO_POLLING_DISABLE   ((uint32_t) 0U)

Write completion auto polling state disable

CSL_OSPI_INTR_MASK_MODE_M_FAIL

#define CSL_OSPI_INTR_MASK_MODE_M_FAIL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_MODE_M_FAIL_FLD_MASK)

Interrupt mask for mode fail interrupt

CSL_OSPI_INTR_MASK_UNDERFLOW_DET

#define CSL_OSPI_INTR_MASK_UNDERFLOW_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_UNDERFLOW_DET_FLD_MASK)

Interrupt mask for underflow detected interrupt

CSL_OSPI_INTR_MASK_IND_OP_DONE

#define CSL_OSPI_INTR_MASK_IND_OP_DONE   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK)

Interrupt mask for complete last triggered indirect operation interrupt

CSL_OSPI_INTR_MASK_IND_RD_REJECT

#define CSL_OSPI_INTR_MASK_IND_RD_REJECT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_READ_REJECT_FLD_MASK)

Interrupt mask for indirect op request rejected interrupt

CSL_OSPI_INTR_MASK_PROT_WR_ATTEMPT

#define CSL_OSPI_INTR_MASK_PROT_WR_ATTEMPT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_MASK)

Interrupt mask for write to protected area rejected interrupt

CSL_OSPI_INTR_MASK_ILLEGAL_ACCESS_DET

#define CSL_OSPI_INTR_MASK_ILLEGAL_ACCESS_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_ILLEGAL_ACCESS_DET_FLD_MASK)

Interrupt mask for illegal AHB access detected interrupt

CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH

#define CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK)

Interrupt mask for indirect transfer watermark level breached interrupt

CSL_OSPI_INTR_MASK_RECV_OVERFLOW_DET

#define CSL_OSPI_INTR_MASK_RECV_OVERFLOW_DET   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RECV_OVERFLOW_FLD_MASK)

Interrupt mask for receive overflow interrupt

CSL_OSPI_INTR_MASK_TX_FIFO_NOT_FULL

#define CSL_OSPI_INTR_MASK_TX_FIFO_NOT_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_TX_FIFO_NOT_FULL_FLD_MASK)

Interrupt mask for small TX FIFO not full interrupt

CSL_OSPI_INTR_MASK_TX_FIFO_FULL

#define CSL_OSPI_INTR_MASK_TX_FIFO_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_TX_FIFO_FULL_FLD_MASK)

Interrupt mask for small TX FIFO full interrupt

CSL_OSPI_INTR_MASK_RX_FIFO_NOT_EMPTY

#define CSL_OSPI_INTR_MASK_RX_FIFO_NOT_EMPTY   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RX_FIFO_NOT_EMPTY_FLD_MASK)

Interrupt mask for small RX FIFO not empty interrupt

CSL_OSPI_INTR_MASK_RX_FIFO_FULL

#define CSL_OSPI_INTR_MASK_RX_FIFO_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_RX_FIFO_FULL_FLD_MASK)

Interrupt mask for small RX FIFO full interrupt

CSL_OSPI_INTR_MASK_IND_RD_SRAM_FULL

#define CSL_OSPI_INTR_MASK_IND_RD_SRAM_FULL   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_MASK)

Interrupt mask for indirect read partion of sram full interrupt

CSL_OSPI_INTR_MASK_POLL_EXP_INT

#define CSL_OSPI_INTR_MASK_POLL_EXP_INT   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_POLL_EXP_INT_FLD_MASK)

Interrupt mask for max num of programmed polls cycles expired interrupt

CSL_OSPI_INTR_MASK_IRQ_STAT_RESV

#define CSL_OSPI_INTR_MASK_IRQ_STAT_RESV   (CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_IRQ_STAT_RESV_FLD_MASK)

Interrupt mask for reserved interrupts

Typedef Documentation

CSL_OspiClkMode

typedef uint32_t CSL_OspiClkMode

CSL_OspiChipSelect

typedef uint32_t CSL_OspiChipSelect

CSL_OspiDecSelect

typedef uint32_t CSL_OspiDecSelect

CSL_OspiMemMapNumAddrBytes

typedef uint32_t CSL_OspiMemMapNumAddrBytes

CSL_OspiPhyOpMode

typedef uint32_t CSL_OspiPhyOpMode

CSL_OspiWriteCompAutoPolling

typedef uint32_t CSL_OspiWriteCompAutoPolling

CSL_OspiIntrMask

typedef uint32_t CSL_OspiIntrMask