Introduction

Macros
#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT (0)

#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_MASK ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT)

#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT (24U)

#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_MASK ((uint32_t)0x1FU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT)

#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT (29U)

#define	CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_MASK ((uint32_t)0x7U<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT)

#define	CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT (0)

#define	CSL_PSILCFG_REG_PEER_CREDIT_CNT_MASK ((uint32_t)0xFFU<<CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT)

#define	CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT (31U)

#define	CSL_PSILCFG_REG_ENABLE_ENABLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT)

#define	CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT (30U)

#define	CSL_PSILCFG_REG_ENABLE_TEARDOWN_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT)

#define	CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT (0)

#define	CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_MASK ((uint32_t)0xFFU<<CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT)

#define	CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT (24U)

#define	CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_MASK ((uint32_t)0x1FU<<CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT)

#define	CSL_PSILCFG_REG_STATIC_TR_X_SHIFT (24U)

#define	CSL_PSILCFG_REG_STATIC_TR_X_MASK (((uint32_t)0x0007U) << CSL_PSILCFG_REG_STATIC_TR_X_SHIFT)

#define	CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT (0U)

#define	CSL_PSILCFG_REG_STATIC_TR_Y_MASK (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT)

#define	CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT (0U)

#define	CSL_PSILCFG_REG_STATIC_TR_Z_MASK (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT)

#define	CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT (1U)

#define	CSL_PSILCFG_REG_RT_ENABLE_IDLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT)

#define	CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT (28U)

#define	CSL_PSILCFG_REG_RT_ENABLE_FLUSH_MASK ((uint32_t)0x01U << CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT)

#define	CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT (29U)

#define	CSL_PSILCFG_REG_RT_ENABLE_PAUSE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT)

#define	CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT (30U)

#define	CSL_PSILCFG_REG_RT_ENABLE_TDOWN_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT)

#define	CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT (31U)

#define	CSL_PSILCFG_REG_RT_ENABLE_ENABLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT (0U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_MASK ((uint32_t)0x0FFFFU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT (16U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT (20U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT (30U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT (31U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT (0U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT (4U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT (8U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT (12U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT (16U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT (20U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT (24U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT (28U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT (0U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT (4U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT (8U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT (12U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT (16U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT (20U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT (24U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT (28U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT (0U)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_MASK ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT (31U)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_MASK ((uint32_t)0x1U<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_PULSE ((uint32_t) 0U)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_RISING_EDGE ((uint32_t) 1U)

PSI-L Configuration Registers
PSI-L Configuration Registers
typedef uint32_t	CSL_PsilCfgReg

#define	CSL_PSILCFG_REG_PEER_THREAD_ID ((uint32_t) 0U)

#define	CSL_PSILCFG_REG_PEER_CREDIT ((uint32_t) 0x001U)

#define	CSL_PSILCFG_REG_ENABLE ((uint32_t) 0x002U)

#define	CSL_PSILCFG_REG_CAPABILITIES ((uint32_t) 0x040U)

#define	CSL_PSILCFG_REG_STATIC_TR ((uint32_t) 0x400U)

#define	CSL_PSILCFG_REG_STATIC_TR_Z ((uint32_t) 0x401U)

#define	CSL_PSILCFG_REG_BYTE_COUNT ((uint32_t) 0x404U)

#define	CSL_PSILCFG_REG_AASRC_FIFO_CFG ((uint32_t) 0x405U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE0 ((uint32_t) 0x406U)

#define	CSL_PSILCFG_REG_AASRC_ORDER_TABLE1 ((uint32_t) 0x407U)

#define	CSL_PSILCFG_REG_RT_ENABLE ((uint32_t) 0x408U)

#define	CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E(N) ((uint32_t)0x4000U + (uint32_t)(N))

Macro Definition Documentation

◆ CSL_PSILCFG_REG_PEER_THREAD_ID

#define CSL_PSILCFG_REG_PEER_THREAD_ID ((uint32_t) 0U)

Peer credit register (implemented for src threads only)

◆ CSL_PSILCFG_REG_PEER_CREDIT

#define CSL_PSILCFG_REG_PEER_CREDIT ((uint32_t) 0x001U)

Enable register

◆ CSL_PSILCFG_REG_ENABLE

#define CSL_PSILCFG_REG_ENABLE ((uint32_t) 0x002U)

Capabilities register

◆ CSL_PSILCFG_REG_CAPABILITIES

#define CSL_PSILCFG_REG_CAPABILITIES ((uint32_t) 0x040U)

Static TR register

◆ CSL_PSILCFG_REG_STATIC_TR

#define CSL_PSILCFG_REG_STATIC_TR ((uint32_t) 0x400U)

Static TR Z register

◆ CSL_PSILCFG_REG_STATIC_TR_Z

#define CSL_PSILCFG_REG_STATIC_TR_Z ((uint32_t) 0x401U)

Byte Count register

◆ CSL_PSILCFG_REG_BYTE_COUNT

#define CSL_PSILCFG_REG_BYTE_COUNT ((uint32_t) 0x404U)

AASRC Tx/Rx FIFO configuration register

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG ((uint32_t) 0x405U)

AASRC Tx/Rx order table 0 register

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0 ((uint32_t) 0x406U)

AASRC Tx/Rx order table 1 register

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1 ((uint32_t) 0x407U)

Realtime enable register

◆ CSL_PSILCFG_REG_RT_ENABLE

#define CSL_PSILCFG_REG_RT_ENABLE ((uint32_t) 0x408U)

Local to global event translation registers Note that these 16 PSIL registers (N=0..15) are only applicable for source thread 0 on PDMA instance pdma_main1 on the AM654x SOC.

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E ( N ) ((uint32_t)0x4000U + (uint32_t)(N))

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT (0)

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_MASK

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_MASK ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT)

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT (24U)

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_MASK

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_MASK ((uint32_t)0x1FU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT)

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT (29U)

◆ CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_MASK

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_MASK ((uint32_t)0x7U<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT)

◆ CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT

#define CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT (0)

◆ CSL_PSILCFG_REG_PEER_CREDIT_CNT_MASK

#define CSL_PSILCFG_REG_PEER_CREDIT_CNT_MASK ((uint32_t)0xFFU<<CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT)

◆ CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT

#define CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT (31U)

◆ CSL_PSILCFG_REG_ENABLE_ENABLE_MASK

#define CSL_PSILCFG_REG_ENABLE_ENABLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT)

◆ CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT

#define CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT (30U)

◆ CSL_PSILCFG_REG_ENABLE_TEARDOWN_MASK

#define CSL_PSILCFG_REG_ENABLE_TEARDOWN_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT)

◆ CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT

#define CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT (0)

◆ CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_MASK

#define CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_MASK ((uint32_t)0xFFU<<CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT)

◆ CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT

#define CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT (24U)

◆ CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_MASK

#define CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_MASK ((uint32_t)0x1FU<<CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT)

◆ CSL_PSILCFG_REG_STATIC_TR_X_SHIFT

#define CSL_PSILCFG_REG_STATIC_TR_X_SHIFT (24U)

◆ CSL_PSILCFG_REG_STATIC_TR_X_MASK

#define CSL_PSILCFG_REG_STATIC_TR_X_MASK (((uint32_t)0x0007U) << CSL_PSILCFG_REG_STATIC_TR_X_SHIFT)

◆ CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT

#define CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT (0U)

◆ CSL_PSILCFG_REG_STATIC_TR_Y_MASK

#define CSL_PSILCFG_REG_STATIC_TR_Y_MASK (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT)

◆ CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT

#define CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT (0U)

◆ CSL_PSILCFG_REG_STATIC_TR_Z_MASK

#define CSL_PSILCFG_REG_STATIC_TR_Z_MASK (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT)

◆ CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT

#define CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT (1U)

◆ CSL_PSILCFG_REG_RT_ENABLE_IDLE_MASK

#define CSL_PSILCFG_REG_RT_ENABLE_IDLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT)

◆ CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT

#define CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT (28U)

◆ CSL_PSILCFG_REG_RT_ENABLE_FLUSH_MASK

#define CSL_PSILCFG_REG_RT_ENABLE_FLUSH_MASK ((uint32_t)0x01U << CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT)

◆ CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT

#define CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT (29U)

◆ CSL_PSILCFG_REG_RT_ENABLE_PAUSE_MASK

#define CSL_PSILCFG_REG_RT_ENABLE_PAUSE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT)

◆ CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT

#define CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT (30U)

◆ CSL_PSILCFG_REG_RT_ENABLE_TDOWN_MASK

#define CSL_PSILCFG_REG_RT_ENABLE_TDOWN_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT)

◆ CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT

#define CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT (31U)

◆ CSL_PSILCFG_REG_RT_ENABLE_ENABLE_MASK

#define CSL_PSILCFG_REG_RT_ENABLE_ENABLE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT (0U)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_MASK

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_MASK ((uint32_t)0x0FFFFU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT (16U)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_MASK

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT (20U)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_MASK

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT (30U)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_MASK

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT (31U)

◆ CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_MASK

#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_MASK ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT (0U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT (4U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT (8U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT (12U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT (16U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT (20U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT (24U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT (28U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT (0U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT (4U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT (8U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT (12U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT (16U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT (20U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT (24U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT (28U)

◆ CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_MASK

#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_MASK ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT (0U)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_MASK

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_MASK ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT (31U)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_MASK

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_MASK ((uint32_t)0x1U<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_PULSE

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_PULSE ((uint32_t) 0U)

◆ CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_RISING_EDGE

#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_RISING_EDGE ((uint32_t) 1U)

Typedef Documentation

◆ CSL_PsilCfgReg

typedef uint32_t CSL_PsilCfgReg

Peer thread ID register (implemented for src threads only)