Introduction

Files
file	uart.h
	This file contains the prototypes of device abstraction layer APIs corresponding to the UART module. This also contains necessary structure, enum and macro definitions and the APIs are consolidated to make them more functional.

Functions
uint32_t	UARTOperatingModeSelect (uint32_t baseAddr, uint32_t modeFlag)
	This API configures the operating mode for the UART instance. The different operating modes are: More...

uint32_t	UARTDivisorValCompute (uint32_t moduleClk, uint32_t baudRate, uint32_t modeFlag, uint32_t mirOverSampRate)
	This API computes the divisor value for the specified operating mode. Not part of this API, the divisor value returned is written to the Divisor Latches to configure the Baud Rate. More...

uint32_t	UARTDivisorLatchWrite (uint32_t baseAddr, uint32_t divisorValue)
	This API is used to write the specified divisor value to Divisor Latch registers DLL and DLH. More...

void	UARTDivisorLatchEnable (uint32_t baseAddr)
	This API enables write access to Divisor Latch registers DLL and DLH. More...

void	UARTDivisorLatchDisable (uint32_t baseAddr)
	This API disables write access to Divisor Latch registers DLL and DLH. More...

uint32_t	UARTRegConfigModeEnable (uint32_t baseAddr, uint32_t modeFlag)
	This API configures the specified Register Configuration mode for the UART. More...

void	UARTRegConfModeRestore (uint32_t baseAddr, uint32_t lcrRegValue)
	This API is used to restore the UART to the specified Register Configuration Mode. More...

void	UARTBreakCtl (uint32_t baseAddr, uint32_t breakState)
	This API is used to introduce or to remove a Break condition. More...

void	UARTLineCharacConfig (uint32_t baseAddr, uint32_t wLenStbFlag, uint32_t parityFlag)
	This API configures the Line Characteristics for the UART instance. The Line Characteristics include: More...

void	UARTParityModeSet (uint32_t baseAddr, uint32_t parityFlag)
	This API configures the Parity feature for the UART. More...

uint32_t	UARTParityModeGet (uint32_t baseAddr)
	This API reads the Parity configuration being set in the UART. More...

void	UARTDMAEnable (uint32_t baseAddr, uint32_t dmaModeFlag)
	This API enables the DMA mode of operation for the UART instance. More...

void	UARTDMADisable (uint32_t baseAddr)
	This API disables the DMA mode of operation. More...

uint32_t	UARTFIFOConfig (uint32_t baseAddr, uint32_t fifoConfig)
	This API configures the FIFO settings for the UART instance. Specifically, this does the following configurations: 1> Configures the Transmitter and Receiver FIFO Trigger Level granularity 2> Configures the Transmitter and Receiver FIFO Trigger Level 3> Configures the bits which clear/not clear the TX and RX FIFOs 4> Configures the DMA mode of operation . More...

uint32_t	UARTEnhanFuncEnable (uint32_t baseAddr)
	This API sets a certain bit in Enhanced Feature Register(EFR) which shall avail the UART to use some Enhanced Features. More...

void	UARTEnhanFuncBitValRestore (uint32_t baseAddr, uint32_t enhanFnBitVal)
	This API restores the ENHANCEDEN bit value of EFR register(EFR[4]) to the corresponding bit value in 'enhanFnBitVal' passed as a parameter to this API. More...

uint32_t	UARTSubConfigMSRSPRModeEn (uint32_t baseAddr)
	This API enables the MSR_SPR Sub-Configuration Mode of operation. More...

uint32_t	UARTSubConfigTCRTLRModeEn (uint32_t baseAddr)
	This API enables the TCR_TLR Sub_Configuration Mode of operation. More...

uint32_t	UARTSubConfigXOFFModeEn (uint32_t baseAddr)
	This API enables the XOFF Sub-Configuration Mode of operation. More...

void	UARTTCRTLRBitValRestore (uint32_t baseAddr, uint32_t tcrTlrBitVal)
	This API restores the TCRTLR bit(MCR[6]) value in Modem Control Register(MCR) to the corresponding bit value in 'tcrTlrBitVal' passed as a parameter to this API. More...

void	UARTIntEnable (uint32_t baseAddr, uint32_t intFlag)
	This API enables the specified interrupts in the UART mode of operation. More...

void	UARTIntDisable (uint32_t baseAddr, uint32_t intFlag)
	This API disables the specified interrupts in the UART mode of operation. More...

void	UARTInt2Enable (uint32_t baseAddr, uint32_t intFlag)
	This API enables the specified interrupts in the UART mode of operation for IER2. More...

void	UARTInt2Disable (uint32_t baseAddr, uint32_t intFlag)
	This API disables the specified interrupts in the UART mode of operation for IER2. More...

uint32_t	UARTSpaceAvail (uint32_t baseAddr)
	This API checks whether the TX FIFO (or THR in non-FIFO mode) is empty or not. More...

uint32_t	UARTCharsAvail (uint32_t baseAddr)
	This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read. More...

uint32_t	UARTCharPutNonBlocking (uint32_t baseAddr, uint8_t byteWrite)
	This API attempts to write a byte into Transmitter Holding Register (THR). It checks only once if the transmitter is empty. More...

int8_t	UARTCharGetNonBlocking (uint32_t baseAddr)
	This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is ready to be read. More...

int8_t	UARTCharGet (uint32_t baseAddr)
	This API waits indefinitely for the arrival of a byte in the receiver FIFO. Once a byte has arrived, it returns that byte. More...

uint8_t	UARTCharGetTimeout (uint32_t baseAddr, uint32_t timeOutVal)
	This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeout value gets decremented to zero, whichever happens first. More...

void	UARTCharPut (uint32_t baseAddr, uint8_t byteTx)
	This API waits indefinitely until the Transmitter FIFO (THR register in non-FIFO mode) and Transmitter Shift Register are empty. On empty, it writes a byte to the THR. More...

void	UARTFIFOCharPut (uint32_t baseAddr, uint8_t byteTx)
	This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter FIFO or the Transmitter Shift Register(TSR). More...

int8_t	UARTFIFOCharGet (uint32_t baseAddr)
	This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding Register(RHR). However before reading the data from RHR, it does not check whether RHR has fresh data or not. More...

uint32_t	UARTFIFOWrite (uint32_t baseAddr, const uint8_t *pBuffer, uint32_t numTxBytes)
	This API copies the requested amount of data from the pointed data block to the UART Transmit FIFO. More...

uint32_t	UARTRxErrorGet (uint32_t baseAddr)
	This API reads the receiver data error status. More...

uint32_t	UARTIntIdentityGet (uint32_t baseAddr)
	This API determines the UART Interrupt Status. More...

uint32_t	UARTIntPendingStatusGet (uint32_t baseAddr)
	This API determines whether any UART interrupt condition is still alive and is pending to be serviced. More...

uint32_t	UARTInt2StatusGet (uint32_t baseAddr)
	This API determines the UART Interrupt Status 2. More...

uint32_t	UARTFIFOEnableStatusGet (uint32_t baseAddr)
	This API determines whether FIFO mode of operation is enabled for the UART instance or not. More...

void	UARTAutoRTSAutoCTSControl (uint32_t baseAddr, uint32_t autoCtsControl, uint32_t autoRtsControl)
	This API controls the use of Auto-RTS and Auto-CTS features which are used in Hardware Flow Control Mode of operation. The Auto-RTS and Auto-CTS functions can be individually enabled or disabled. More...

void	UARTSpecialCharDetectControl (uint32_t baseAddr, uint32_t controlFlag)
	This API controls the feature of detecting a Special Character arriving in the receiver. More...

void	UARTSoftwareFlowCtrlOptSet (uint32_t baseAddr, uint32_t swFlowCtrl)
	This API configures the options for Software Flow Control. More...

void	UARTHardwareFlowCtrlOptSet (uint32_t baseAddr, uint32_t hwFlowCtrl)
	This API configures the options for hardware Flow Control. More...

void	UARTPulseShapingControl (uint32_t baseAddr, uint32_t shapeControl)
	Used only in UART mode, this API is used to control the pulse shaping feature. Pulse shaping feature could either be enabled or disabled in UART mode. More...

void	UARTModuleReset (uint32_t baseAddr)
	This API performs a module reset of the UART instance. It also waits until the reset process is complete. More...

void	UARTIdleModeConfigure (uint32_t baseAddr, uint32_t modeFlag)
	This API can be used to control the Power Management request/acknowledgement process. More...

void	UARTWakeUpControl (uint32_t baseAddr, uint32_t controlFlag)
	This API is used to control(enable/disable) the Wake-Up feature of the UART. More...

void	UARTAutoIdleModeControl (uint32_t baseAddr, uint32_t modeFlag)
	This API is used to control(enable/disable) the Auto-Idle mode of operation of the UART. More...

void	UARTFlowCtrlTrigLvlConfig (uint32_t baseAddr, uint32_t rtsHaltFlag, uint32_t rtsStartFlag)
	This API configures the Receiver FIFO threshold level to start/stop transmission during Hardware Flow Control. More...

void	UARTXON1XOFF1ValProgram (uint32_t baseAddr, uint8_t xon1Value, uint8_t xoff1Value)
	This API programs the XON1/ADDR1 and XOFF1 registers. More...

void	UARTXON2XOFF2ValProgram (uint32_t baseAddr, uint8_t xon2Value, uint8_t xoff2Value)
	This API programs the XON2/ADDR2 and XOFF2 registers. More...

void	UARTXONAnyFeatureControl (uint32_t baseAddr, uint32_t controlFlag)
	This API controls(enables/disables) the XON-any feature in Modem Control Register(MCR). More...

void	UARTLoopbackModeControl (uint32_t baseAddr, uint32_t controlFlag)
	This API controls(enables/disables) the Loopback mode of operation for the UART instance. More...

void	UARTModemControlSet (uint32_t baseAddr, uint32_t modeFlag)
	This API switches the specified Modem Control Signals to active state. The Modem Control signals in context are DCD, RI, RTS and DTR. More...

void	UARTModemControlClear (uint32_t baseAddr, uint32_t modeFlag)
	This API switches the specified Modem Control signals to inactive state. The Modem Control signals in context are DCD, RI, RTS and DTR. More...

uint32_t	UARTModemStatusGet (uint32_t baseAddr)
	This API reads the values on Modem Signal Lines. The Modem Signals in context are: 1> Data Carrier Detect(DCD) 2> Ring Indicator(RI) 3> Data Set Ready(DSR) 4> Clear To Send(CTS) . More...

uint32_t	UARTModemStatusChangeCheck (uint32_t baseAddr)
	This API determines if the values on Modem Signal Lines have changed since the last read of Modem Status Register(MSR). The Modem Signals in context are DCD, RI, DSR, CTS. More...

void	UARTResumeOperation (uint32_t baseAddr)
	This API reads the RESUME register which clears the internal flags. More...

void	UARTWakeUpEventsEnable (uint32_t baseAddr, uint32_t wakeUpFlag)
	This API enables the Wake-Up capability for the specified events. On enabling Wake-Up capability for them, the occurence of the corresponding event shall wake up the system. More...

void	UARTWakeUpEventsDisable (uint32_t baseAddr, uint32_t wakeUpFlag)
	This API disables the Wake-Up capability for the specified events. On disabling Wake-Up capability for them, the occurence of the corresponding event shall not wake up the system. More...

void	UARTFIFOTrigLvlGranControl (uint32_t baseAddr, uint32_t rxFIFOGranCtrl, uint32_t txFIFOGranCtrl)
	This API controls the feature of setting the Trigger Level granularity as 1 for Transmitter and Receiver FIFOs. More...

void	UARTDSRInterruptControl (uint32_t baseAddr, uint32_t controlFlag)
	This API controls the interrupt enable and disable feature for Data Set Ready(DSRn) interrupt. More...

void	UARTTxEmptyIntControl (uint32_t baseAddr, uint32_t controlFlag)
	This API is used to choose a condition under which a Transmit Holding Register(THR) Interrupt should occur. A THR interrupt can be configured to occur either when: 1> TX FIFO becoming empty OR 2> TX FIFO and TX Shift register becoming empty. More...

void	UARTRXCTSDSRWakeUpConfigure (uint32_t baseAddr, uint32_t wakeUpFlag)
	This API controls (enables/disables) a feature where a falling edge on the RX, CTSn or DSRs could send a wake-up interrupt to the CPU. More...

uint32_t	UARTRXCTSDSRTransitionStatusGet (uint32_t baseAddr)
	This API determines whether a falling edge occured on RX, CTSn or DSRn lines. More...

void	UARTDMACounterResetControl (uint32_t baseAddr, uint32_t controlFlag)
	This API controls the DMA Counter Reset options. More...

uint32_t	UARTTxFIFOFullStatusGet (uint32_t baseAddr)
	This API determines whether the Transmitter FIFO is full or not. More...

uint32_t	UARTTxFIFOLevelGet (uint32_t baseAddr)
	This API determines the current level of the Transmitter FIFO. More...

uint32_t	UARTRxFIFOLevelGet (uint32_t baseAddr)
	This API determines the current level of the Receiver FIFO. More...

uint32_t	UARTAutobaudParityGet (uint32_t baseAddr)
	This API determines the Parity mode being configured by the system in the UART Autobauding mode. More...

uint32_t	UARTAutobaudWordLenGet (uint32_t baseAddr)
	This API determines the word length per frame(character length) being configured by the system in UART Autobauding mode. More...

uint32_t	UARTAutobaudSpeedGet (uint32_t baseAddr)
	This API determines the baud rate being configured by the system in UART Autobauding mode. More...

void	UARTScratchPadRegWrite (uint32_t baseAddr, uint32_t scratchValue)
	This API programs the Scratchpad Register with the specified value. More...

uint32_t	UARTScratchPadRegRead (uint32_t baseAddr)
	This API reads the value in Scratchpad Register. More...

uint32_t	UARTModuleVersionNumberGet (uint32_t baseAddr)
	This API reads the Revision Number of the module from the Module Version Register(MVR). More...

void	UARTFIFORegisterWrite (uint32_t baseAddr, uint32_t fcrValue)
	This API is used to write a specified value to the FIFO Control Register(FCR). More...

void	UARTTxDMAThresholdControl (uint32_t baseAddr, uint32_t thrsCtrlFlag)
	This function controls the method of setting the Transmit DMA Threshold Value. The Transmit DMA Threshold Value can be set to a default value of 64 characters or can take the value in TX_DMA_THRESHOLD register. More...

void	UARTTxDMAThresholdValConfig (uint32_t baseAddr, uint32_t thrsValue)
	This function programs the TX_DMA_THRESHOLD register which holds Transmit DMA Threshold value to be used. When a TX DMA Threshold value other than 64 characters is required, this function can be used to program the same. More...

void	UARTFIFOLevelSet (uint32_t baseAddr, uint32_t rxLevel)
	This function sets the receiver FIFO trigger level. . More...

uint32_t	UARTModemControlGet (uint32_t baseAddr)
	This function gets the status of the RTS and AFE bits in the MCR register. More...

void	UARTFIFOCtrlRegWrite (uint32_t baseAddr, uint32_t fcrValue)
	This API is used to write a specified value to the FIFO Control Register(FCR) without disabling the divisor values. Preferable setting FCR during runtime. More...

void	UARTModemControlReset (uint32_t baseAddr)
	This API resets the Modem control register. More...

uint32_t	UARTReadStatus (uint32_t baseAddr)
	This API reads the line status register value. More...

uint32_t	UARTIsTransmitterEmpty (uint32_t baseAddr)
	This API returns the transmitter empty status i.e. if Transmitter FIFO (THR register in non-FIFO mode) and Transmitter Shift Register are empty. More...

uint32_t	UARTCharGetNonBlocking2 (uint32_t baseAddr, uint8_t *pChar)
	This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is ready to be read. More...

uint32_t	UARTCharGetTimeout2 (uint32_t baseAddr, uint32_t timeOutVal, uint8_t *pChar)
	This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeout value gets decremented to zero, whichever happens first.This is a replacement for the UARTCharGetTimeout which will incorrectly return timeout if the UART receives 0xFF as data. More...

void	UARTDirPolSet (uint32_t baseAddr, uint32_t dirPol)
	This API is used to set the RS-485 External Transceiver Direction Polarity. More...

void	UARTDirEnControl (uint32_t baseAddr, uint32_t dirEnFlag)
	This API is used to control the RS-485 External Transceiver Direction. More...

void	UARTSetTimeOutValue (uint32_t baseAddr, uint16_t timeoutIntrVal, uint32_t timeoutBehavior)
	This API is used to set the timeout value and the TIMEOUT_BEHAVE. More...

The size of the Transmitter FIFO.
#define	TX_FIFO_SIZE (64)

The size of the Receiver FIFO.
#define	RX_FIFO_SIZE (64)

Values to configure the Operating modes of UART.
#define	UART16x_OPER_MODE (UART_MDR1_MODE_SELECT_UART16X)

#define	UART_SIR_OPER_MODE (UART_MDR1_MODE_SELECT_SIR)

#define	UART16x_AUTO_BAUD_OPER_MODE (UART_MDR1_MODE_SELECT_UART16XAUTO)

#define	UART13x_OPER_MODE (UART_MDR1_MODE_SELECT_UART13X)

#define	UART_MIR_OPER_MODE (UART_MDR1_MODE_SELECT_MIR)

#define	UART_FIR_OPER_MODE (UART_MDR1_MODE_SELECT_FIR)

#define	UART_CIR_OPER_MODE (UART_MDR1_MODE_SELECT_CIR)

#define	UART_DISABLED_MODE (UART_MDR1_MODE_SELECT_MASK)

Values to configure Timeout Behaviour for UART.
#define	UART_TIMEOUT_COUNTER_RESET (0U)

#define	UART_TIMEOUT_COUNTER_NO_CHANGE (1U)

Values to control the Line characteristics.
#define	UART_BREAK_COND_DISABLE

#define	UART_BREAK_COND_ENABLE

Values to control parity feature.
#define	UART_PARITY_REPR_1

#define	UART_PARITY_REPR_0

#define	UART_ODD_PARITY

#define	UART_EVEN_PARITY

#define	UART_PARITY_NONE

#define	UART_FRAME_NUM_STB_1
	Number of Stop Bits per frame. More...

#define	UART_FRAME_NUM_STB_1_5_2

#define	UART_FRAME_WORD_LENGTH_5
	Word Length per frame. More...

#define	UART_FRAME_WORD_LENGTH_6

#define	UART_FRAME_WORD_LENGTH_7

#define	UART_FRAME_WORD_LENGTH_8

Values associated with setting the Trigger Levels and DMA mode
selection.
#define	UART_FCR_RX_TRIG_LVL_8
	Values for trigger level for the Receiver FIFO. More...

#define	UART_FCR_RX_TRIG_LVL_16

#define	UART_FCR_RX_TRIG_LVL_56

#define	UART_FCR_RX_TRIG_LVL_60

#define	UART_FCR_TX_TRIG_LVL_8
	Values for the trigger level for the Transmitter FIFO. More...

#define	UART_FCR_TX_TRIG_LVL_16

#define	UART_FCR_TX_TRIG_LVL_32

#define	UART_FCR_TX_TRIG_LVL_56

#define	UART_DMA_MODE_0_ENABLE
	Values corresponding to DMA mode selection. More...

#define	UART_DMA_MODE_1_ENABLE

#define	UART_DMA_MODE_2_ENABLE

#define	UART_DMA_MODE_3_ENABLE

#define	UART_DMA_EN_PATH_FCR
	Values used to choose the path for configuring the DMA Mode. DMA Mode could be configured either through FCR or SCR. More...

#define	UART_DMA_EN_PATH_SCR

Values related to enabling/disabling of Interrupts.
#define	UART_INT_CTS (UART_IER_CTS_IT_MASK)
	Values for enabling/disabling the interrupts of UART. More...

#define	UART_INT_RTS (UART_IER_RTS_IT_MASK)

#define	UART_INT_XOFF (UART_IER_XOFF_IT_MASK)

#define	UART_INT_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)

#define	UART_INT_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)

#define	UART_INT_LINE_STAT (UART_IER_LINE_STS_IT_MASK)

#define	UART_INT_THR (UART_IER_THR_IT_MASK)

#define	UART_INT_RHR_CTI (UART_IER_RHR_IT_MASK)

#define	UART_INT2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)

#define	UART_INT2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)

Values related to Line Status information.
#define	UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
	Values pertaining to UART Line Status information. More...

#define	UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)

#define	UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)

#define	UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)

#define	UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)

Values related to status of Interrupt souces.
#define	UART_INTID_MODEM_STAT
	Values pertaining to status of UART Interrupt sources. More...

#define	UART_INTID_TX_THRES_REACH

#define	UART_INTID_RX_THRES_REACH

#define	UART_INTID_RX_LINE_STAT_ERROR

#define	UART_INTID_CHAR_TIMEOUT

#define	UART_INTID_XOFF_SPEC_CHAR_DETECT

#define	UART_INTID_MODEM_SIG_STATE_CHANGE

#define	UART_INT_PENDING (0U)
	Values indicating the UART Interrupt pending status. More...

#define	UART_N0_INT_PENDING (1U)

Values pertaining to control of Enhanced Features.
#define	UART_AUTO_CTS_ENABLE
	Values for controlling Auto-CTS and Auto-RTS features. More...

#define	UART_AUTO_CTS_DISABLE

#define	UART_AUTO_RTS_ENABLE

#define	UART_AUTO_RTS_DISABLE

#define	UART_SPECIAL_CHAR_DETECT_ENABLE (UART_EFR_SPECIAL_CHAR_DETECT_MASK)
	Values to enable/disable detection of Special Character. More...

#define	UART_SPECIAL_CHAR_DETECT_DISABLE

#define	UART_NO_SOFTWARE_FLOW_CONTROL
	Values to configure the options for Software Flow Control. More...

#define	UART_TX_RX_XON1_XOFF1

#define	UART_TX_RX_XON2_XOFF2

#define	UART_TX_RX_XON1_XOFF1_XON2_XOFF2

#define	UART_NO_HARDWARE_FLOW_CONTROL UART_EFR_HW_NO_FLOW_CONTROL_VALUE

#define	UART_RTS_ENABLE UART_EFR_HW_ENABLE_RTS_VALUE

#define	UART_CTS_ENABLE UART_EFR_HW_ENALE_CTS_VALUE

#define	UART_RTS_CTS_ENABLE UART_EFR_HW_ENABLE_RTS_CTS_FLOW_CONTROL_VALUE

Values corresponding to Mode Definition Register 2(MDR2).
#define	UART_PULSE_NORMAL
	Values to enable/disable Pulse shaping for UART. More...

#define	UART_PULSE_SHAPING

Values corresponding to Mode Definition Register 3(MDR3).
#define	UART_TX_DMA_THRESHOLD_64
	Values used to control the method of setting the TX DMA Threshold value. More...

#define	UART_TX_DMA_THRESHOLD_REG

Macros related to control and status of Modem Signals.
#define	UART_XON_ANY_ENABLE
	Values to enable/disable XON any feature. More...

#define	UART_XON_ANY_DISABLE

#define	UART_LOOPBACK_MODE_ENABLE
	Values to enable/disable Loopback mode of operation. More...

#define	UART_LOOPBACK_MODE_DISABLE

#define	UART_DCD_CONTROL (UART_MCR_CD_STS_CH_MASK)
	Macros used to force the Modem Control lines to active/inactive states. More...

#define	UART_RI_CONTROL (UART_MCR_RI_STS_CH_MASK)

#define	UART_RTS_CONTROL (UART_MCR_RTS_MASK)

#define	UART_DTR_CONTROL (UART_MCR_DTR_MASK)

#define	UART_DCD_VALUE (UART_MSR_NCD_STS_MASK)
	Values that indicate the values on Modem Control lines. More...

#define	UART_RI_VALUE (UART_MSR_NRI_STS_MASK)

#define	UART_DSR_VALUE (UART_MSR_NDSR_STS_MASK)

#define	UART_CTS_VALUE (UART_MSR_NCTS_STS_MASK)

#define	UART_DCD_STS_CHANGED (UART_MSR_DCD_STS_MASK)
	Values used to detect the changes in Modem Control lines. More...

#define	UART_RI_STS_CHANGED (UART_MSR_RI_STS_MASK)

#define	UART_DSR_STS_CHANGED (UART_MSR_DSR_STS_MASK)

#define	UART_CTS_STS_CHANGED (UART_MSR_CTS_STS_MASK)

Values related to the control and status of Supplementary registers.
#define	UART_RX_TRIG_LVL_GRAN_1_DISABLE
	Values used to enable/disable a granularity of 1 for TX and RX FIFO triggerlevels. More...

#define	UART_RX_TRIG_LVL_GRAN_1_ENABLE

#define	UART_TX_TRIG_LVL_GRAN_1_DISABLE

#define	UART_TX_FIFO_LVL_GRAN_1_ENABLE

#define	UART_DSRn_INT_DISABLE
	Value used to enable/disable DSRn interrupt. More...

#define	UART_DSRn_INT_ENABLE

#define	UART_RX_CTS_DSR_WAKEUP_DISABLE
	Values to control the module Wake-Up rights for RX, CTSn and DSRn pins. More...

#define	UART_RX_CTS_DSR_WAKEUP_ENABLE

#define	UART_THR_INT_NORMAL
	Values to control the THR interrupt modes. More...

#define	UART_THR_INT_FIFO_TSR_EMPTY

#define	UART_DMA_CNTR_NO_RESET_FIFO_RESET
	Values to control the DMA counter reset features. More...

#define	UART_DMA_CNTR_RESET_FIFO_RESET

#define	UART_RX_CTS_DSR_NO_FALL_EDGE
	Values indicating the Falling edge status on RX, CTSn and DSRn pins. More...

#define	UART_RX_CTS_DSR_FALL_EDGE

#define	UART_TX_FIFO_NOT_FULL
	Values indicating the filled status of TX FIFO. More...

#define	UART_TX_FIFO_FULL

Values related to Auxilliary Control Register(ACREG).
#define	UART_SD_PIN_LOW
	Values to set/clear the SD pin. More...

#define	UART_SD_PIN_HIGH

Values controlling System Configuration functions.
#define	UART_IDLEMODE_FORCE_IDLE
	Values controlling Power Management Request/Acknowledgement modes. More...

#define	UART_IDLEMODE_NO_IDLE

#define	UART_IDLEMODE_SMART_IDLE

#define	UART_IDLEMODE_SMART_IDLE_WAKEUP

#define	UART_WAKEUP_ENABLE
	Values enabling/disabling WakeUp capability. More...

#define	UART_WAKEUP_DISABLE

#define	UART_AUTO_IDLE_MODE_ENABLE
	Values to enable /disable Autoidle mode. More...

#define	UART_AUTO_IDLE_MODE_DISABLE

Values configuring Wake-up modes for the UART in Wake-Up Enable
Register.
#define	UART_WAKEUP_TX_INTERRUPT (UART_WER_EVENT_7_TX_WAKEUP_EN_MASK)
	Values that enable/disable Wake-Up generation ability for various signals. More...

#define	UART_WAKEUP_RLS_INTERRUPT

#define	UART_WAKEUP_RHR_INTERRUPT

#define	UART_WAKEUP_RX_ACTIVITY (UART_WER_EVENT_4_RX_ACTIVITY_MASK)

#define	UART_WAKEUP_DCD_ACTIVITY

#define	UART_WAKEUP_RI_ACTIVITY (UART_WER_EVENT_2_RI_ACTIVITY_MASK)

#define	UART_WAKEUP_DSR_ACTIVITY (UART_WER_EVENT_1_DSR_ACTIVITY_MASK)

#define	UART_WAKEUP_CTS_ACTIVITY (UART_WER_EVENT_0_CTS_ACTIVITY_MASK)

Values indicating the line characteristics of UART Autobauding mode
communication.
#define	UART_AUTOBAUD_NO_PARITY
	Values indicating the parity in UART Autobauding mode. More...

#define	UART_AUTOBAUD_PARITY_SPACE

#define	UART_AUTOBAUD_EVEN_PARITY

#define	UART_AUTOBAUD_ODD_PARITY

#define	UART_AUTOBAUD_CHAR_LENGTH_7
	Values indicating the word length in UART Autobaud mode. More...

#define	UART_AUTOBAUD_CHAR_LENGTH_8

#define	UART_AUTOBAUD_NO_SPEED_IDEN (UART_UASR_SPEED_SPEED_VALUE_0)
	Values indicating the baud rate in UART Autobaud mode. More...

#define	UART_AUTOBAUD_SPEED_115200 (UART_UASR_SPEED_SPEED_VALUE_1)

#define	UART_AUTOBAUD_SPEED_57600 (UART_UASR_SPEED_SPEED_VALUE_2)

#define	UART_AUTOBAUD_SPEED_38400 (UART_UASR_SPEED_SPEED_VALUE_3)

#define	UART_AUTOBAUD_SPEED_28800 (UART_UASR_SPEED_SPEED_VALUE_4)

#define	UART_AUTOBAUD_SPEED_19200 (UART_UASR_SPEED_SPEED_VALUE_5)

#define	UART_AUTOBAUD_SPEED_14400 (UART_UASR_SPEED_SPEED_VALUE_6)

#define	UART_AUTOBAUD_SPEED_9600 (UART_UASR_SPEED_SPEED_VALUE_7)

#define	UART_AUTOBAUD_SPEED_4800 (UART_UASR_SPEED_SPEED_VALUE_8)

#define	UART_AUTOBAUD_SPEED_2400 (UART_UASR_SPEED_SPEED_VALUE_9)

#define	UART_AUTOBAUD_SPEED_1200 (UART_UASR_SPEED_SPEED_VALUE_10)

Miscellaneous macros.
#define	UART_TRIG_LVL_GRANULARITY_4 ((uint32_t) 0x0000U)
	Values used to choose the trigger level granularity. More...

#define	UART_TRIG_LVL_GRANULARITY_1 ((uint32_t) 0x0001U)

#define	UART_REG_CONFIG_MODE_A (uint32_t) (0x0080)
	Values to be used while switching between register configuration modes. More...

#define	UART_REG_CONFIG_MODE_B (uint32_t) (0x00BF)

#define	UART_REG_OPERATIONAL_MODE (uint32_t) (0x007F)

#define	UART_FIFO_CONFIG(txGra, rxGra, txTrig, rxTrig, txClr, rxClr, dmaEnPath, dmaMode)
	Parameterized macro to configure the FIFO settings. More...

#define	UART_FCR_PROGRAM(rxFIFOTrig, txFIFOTrig, dmaMode, txClr, rxClr, fifoEn)
	Parameterized macro used to determine a value to be written to FCR. More...

#define	UART_FIFO_CONFIG_TXGRA ((uint32_t) 0xFU << 26)

#define	UART_FIFO_CONFIG_RXGRA ((uint32_t) 0xFU << 22)

#define	UART_FIFO_CONFIG_TXTRIG ((uint32_t) 0xFFU << 14)

#define	UART_FIFO_CONFIG_RXTRIG ((uint32_t) 0xFFU << 6)

#define	UART_FIFO_CONFIG_TXCLR ((uint32_t) 0x1U << 5)

#define	UART_FIFO_CONFIG_RXCLR ((uint32_t) 0x1U << 4)

#define	UART_FIFO_CONFIG_DMAENPATH ((uint32_t) 0x1U << 3)

#define	UART_FIFO_CONFIG_DMAMODE ((uint32_t) 0x7U << 0)

#define	UART_MIR_OVERSAMPLING_RATE_41 ((uint32_t) 41U)
	Over-sampling rate for MIR mode used to obtain the Divisor Values. More...

#define	UART_MIR_OVERSAMPLING_RATE_42 ((uint32_t) 42U)

#define	UART_FCR_TX_FIFO_TRIG_8SPACES ((uint32_t) 0x0U)

#define	UART_FCR_TX_FIFO_TRIG_16SPACES ((uint32_t) 0x1U)

#define	UART_FCR_TX_FIFO_TRIG_32SPACES ((uint32_t) 0x2U)

#define	UART_FCR_TX_FIFO_TRIG_56SPACES ((uint32_t) 0x3U)

#define	UART_LCR_STB_SHIFT ((uint32_t) 0x00000002U)
	used in uart console init function More...

#define	UART_LCR_PEN_SHIFT ((uint32_t) 0x00000003U)

#define	UART_LCR_BC_SHIFT ((uint32_t) 0x00000006U)

#define	UART_LCR_PARITY_EN_DISABLE ((uint32_t) 0x0U)

#define	UART_MDR1_MODE_SELECT_CIR ((uint32_t) 0x6U)

#define	UART_MDR1_MODE_SELECT_DISABLED ((uint32_t) 0x7U)

#define	UART_MDR1_MODE_SELECT_FIR ((uint32_t) 0x5U)

#define	UART_MDR1_MODE_SELECT_MIR ((uint32_t) 0x4U)

#define	UART_MDR1_MODE_SELECT_SIR ((uint32_t) 0x1U)

#define	UART_MDR1_MODE_SELECT_UART13X ((uint32_t) 0x3U)

#define	UART_MDR1_MODE_SELECT_UART16X ((uint32_t) 0x0U)

#define	UART_MDR1_MODE_SELECT_UART16XAUTO ((uint32_t) 0x2U)

#define	UART_FCR_RX_FIFO_TRIG_16CHAR ((uint32_t) 0x1U)

#define	UART_FCR_RX_FIFO_TRIG_56CHAR ((uint32_t) 0x2U)

#define	UART_FCR_RX_FIFO_TRIG_60CHAR ((uint32_t) 0x3U)

#define	UART_FCR_RX_FIFO_TRIG_8CHAR ((uint32_t) 0x0U)

#define	UART_EFR_SW_FLOW_CONTROL_RX_SHIFT ((uint32_t) 0x0U)

#define	UART_EFR_SW_FLOW_CONTROL_TX_SHIFT ((uint32_t) 0x2U)

#define	UART_MDR3_SET_DMA_TX_THRESHOLD_64 ((uint32_t) 0x0U)
	macros used to determine a value to be written to MDR3. More...

#define	UART_MDR3_SET_DMA_TX_THRESHOLD_REG ((uint32_t) 0x1U)

#define	UART_MDR3_DIR_POL_0 ((uint32_t) 0U)

#define	UART_MDR3_DIR_POL_1 ((uint32_t) 1U)

Macro Definition Documentation

◆ TX_FIFO_SIZE

#define TX_FIFO_SIZE (64)

◆ RX_FIFO_SIZE

#define RX_FIFO_SIZE (64)

◆ UART16x_OPER_MODE

#define UART16x_OPER_MODE (UART_MDR1_MODE_SELECT_UART16X)

◆ UART_SIR_OPER_MODE

#define UART_SIR_OPER_MODE (UART_MDR1_MODE_SELECT_SIR)

◆ UART16x_AUTO_BAUD_OPER_MODE

#define UART16x_AUTO_BAUD_OPER_MODE (UART_MDR1_MODE_SELECT_UART16XAUTO)

◆ UART13x_OPER_MODE

#define UART13x_OPER_MODE (UART_MDR1_MODE_SELECT_UART13X)

◆ UART_MIR_OPER_MODE

#define UART_MIR_OPER_MODE (UART_MDR1_MODE_SELECT_MIR)

◆ UART_FIR_OPER_MODE

#define UART_FIR_OPER_MODE (UART_MDR1_MODE_SELECT_FIR)

◆ UART_CIR_OPER_MODE

#define UART_CIR_OPER_MODE (UART_MDR1_MODE_SELECT_CIR)

◆ UART_DISABLED_MODE

#define UART_DISABLED_MODE (UART_MDR1_MODE_SELECT_MASK)

◆ UART_TIMEOUT_COUNTER_RESET

#define UART_TIMEOUT_COUNTER_RESET (0U)

◆ UART_TIMEOUT_COUNTER_NO_CHANGE

#define UART_TIMEOUT_COUNTER_NO_CHANGE (1U)

◆ UART_BREAK_COND_DISABLE

#define UART_BREAK_COND_DISABLE

Value:

(UART_LCR_BREAK_EN_BREAK_EN_VALUE_0 \
                                             <<                                 \
                                             UART_LCR_BREAK_EN_SHIFT)

Break condition generation controls.

◆ UART_BREAK_COND_ENABLE

#define UART_BREAK_COND_ENABLE

Value:

(UART_LCR_BREAK_EN_BREAK_EN_VALUE_1 \
                                             <<                                 \
                                             UART_LCR_BREAK_EN_SHIFT)

◆ UART_PARITY_REPR_1

#define UART_PARITY_REPR_1

Value:

(UART_LCR_PARITY_TYPE2_MASK |                   \
                                             (                                              \
                                                 UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_0 \
                                                 <<                                         \
                                                 UART_LCR_PARITY_TYPE1_SHIFT) |             \
                                             UART_LCR_PARITY_EN_MASK)

◆ UART_PARITY_REPR_0

#define UART_PARITY_REPR_0

Value:

(UART_LCR_PARITY_TYPE2_MASK |                   \
                                             (                                              \
                                                 UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_1 \
                                                 <<                                         \
                                                 UART_LCR_PARITY_TYPE1_SHIFT) |             \
                                             UART_LCR_PARITY_EN_MASK)

◆ UART_ODD_PARITY

#define UART_ODD_PARITY

Value:

((                                              \
                                                 UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_0 \
                                                 <<                                         \
                                                 UART_LCR_PARITY_TYPE1_SHIFT) |             \
                                             UART_LCR_PARITY_EN_MASK)

◆ UART_EVEN_PARITY

#define UART_EVEN_PARITY

Value:

((                                              \
                                                 UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_1 \
                                                 <<                                         \
                                                 UART_LCR_PARITY_TYPE1_SHIFT) |             \
                                             UART_LCR_PARITY_EN_MASK)

◆ UART_PARITY_NONE

#define UART_PARITY_NONE

Value:

(   \
        UART_LCR_PARITY_EN_PARITY_EN_VALUE_0 << \
        UART_LCR_PARITY_EN_SHIFT)

◆ UART_FRAME_NUM_STB_1

#define UART_FRAME_NUM_STB_1

Value:

(UART_LCR_NB_STOP_NB_STOP_VALUE_0 \
                                             <<                               \
                                             UART_LCR_NB_STOP_SHIFT)

Number of Stop Bits per frame.

◆ UART_FRAME_NUM_STB_1_5_2

#define UART_FRAME_NUM_STB_1_5_2

Value:

(UART_LCR_NB_STOP_NB_STOP_VALUE_1 \
                                             <<                               \
                                             UART_LCR_NB_STOP_SHIFT)

◆ UART_FRAME_WORD_LENGTH_5

#define UART_FRAME_WORD_LENGTH_5

Value:

( \

UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_0)

Word Length per frame.

◆ UART_FRAME_WORD_LENGTH_6

#define UART_FRAME_WORD_LENGTH_6

Value:

( \

UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_1)

◆ UART_FRAME_WORD_LENGTH_7

#define UART_FRAME_WORD_LENGTH_7

Value:

( \

UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_2)

◆ UART_FRAME_WORD_LENGTH_8

#define UART_FRAME_WORD_LENGTH_8

Value:

( \

UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_3)

◆ UART_FCR_RX_TRIG_LVL_8

#define UART_FCR_RX_TRIG_LVL_8

Value:

(UART_FCR_RX_FIFO_TRIG_8CHAR << \

UART_FCR_RX_FIFO_TRIG_SHIFT)

UART_FCR_RX_FIFO_TRIG_8CHAR

#define UART_FCR_RX_FIFO_TRIG_8CHAR

Definition: uart.h:742

Values for trigger level for the Receiver FIFO.

◆ UART_FCR_RX_TRIG_LVL_16

#define UART_FCR_RX_TRIG_LVL_16

Value:

(UART_FCR_RX_FIFO_TRIG_16CHAR << \

UART_FCR_RX_FIFO_TRIG_SHIFT)

UART_FCR_RX_FIFO_TRIG_16CHAR

#define UART_FCR_RX_FIFO_TRIG_16CHAR

Definition: uart.h:739

◆ UART_FCR_RX_TRIG_LVL_56

#define UART_FCR_RX_TRIG_LVL_56

Value:

(UART_FCR_RX_FIFO_TRIG_56CHAR << \

UART_FCR_RX_FIFO_TRIG_SHIFT)

UART_FCR_RX_FIFO_TRIG_56CHAR

#define UART_FCR_RX_FIFO_TRIG_56CHAR

Definition: uart.h:740

◆ UART_FCR_RX_TRIG_LVL_60

#define UART_FCR_RX_TRIG_LVL_60

Value:

(UART_FCR_RX_FIFO_TRIG_60CHAR << \

UART_FCR_RX_FIFO_TRIG_SHIFT)

UART_FCR_RX_FIFO_TRIG_60CHAR

#define UART_FCR_RX_FIFO_TRIG_60CHAR

Definition: uart.h:741

◆ UART_FCR_TX_TRIG_LVL_8

#define UART_FCR_TX_TRIG_LVL_8

Value:

(UART_FCR_TX_FIFO_TRIG_8SPACES << \

UART_FCR_TX_FIFO_TRIG_SHIFT)

UART_FCR_TX_FIFO_TRIG_8SPACES

#define UART_FCR_TX_FIFO_TRIG_8SPACES

Definition: uart.h:718

Values for the trigger level for the Transmitter FIFO.

◆ UART_FCR_TX_TRIG_LVL_16

#define UART_FCR_TX_TRIG_LVL_16

Value:

(UART_FCR_TX_FIFO_TRIG_16SPACES << \

UART_FCR_TX_FIFO_TRIG_SHIFT)

UART_FCR_TX_FIFO_TRIG_16SPACES

#define UART_FCR_TX_FIFO_TRIG_16SPACES

Definition: uart.h:719

◆ UART_FCR_TX_TRIG_LVL_32

#define UART_FCR_TX_TRIG_LVL_32

Value:

(UART_FCR_TX_FIFO_TRIG_32SPACES << \

UART_FCR_TX_FIFO_TRIG_SHIFT)

UART_FCR_TX_FIFO_TRIG_32SPACES

#define UART_FCR_TX_FIFO_TRIG_32SPACES

Definition: uart.h:720

◆ UART_FCR_TX_TRIG_LVL_56

#define UART_FCR_TX_TRIG_LVL_56

Value:

(UART_FCR_TX_FIFO_TRIG_56SPACES << \

UART_FCR_TX_FIFO_TRIG_SHIFT)

UART_FCR_TX_FIFO_TRIG_56SPACES

#define UART_FCR_TX_FIFO_TRIG_56SPACES

Definition: uart.h:721

◆ UART_DMA_MODE_0_ENABLE

#define UART_DMA_MODE_0_ENABLE

Value:

( \

UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_0)

Values corresponding to DMA mode selection.

◆ UART_DMA_MODE_1_ENABLE

#define UART_DMA_MODE_1_ENABLE

Value:

( \

UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_1)

◆ UART_DMA_MODE_2_ENABLE

#define UART_DMA_MODE_2_ENABLE

Value:

( \

UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_2)

◆ UART_DMA_MODE_3_ENABLE

#define UART_DMA_MODE_3_ENABLE

Value:

( \

UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_3)

◆ UART_DMA_EN_PATH_FCR

#define UART_DMA_EN_PATH_FCR

Value:

( \

UART_SCR_DMA_MODE_CTL_DMA_MODE_CTL_VALUE_0)

Values used to choose the path for configuring the DMA Mode. DMA Mode could be configured either through FCR or SCR.

◆ UART_DMA_EN_PATH_SCR

#define UART_DMA_EN_PATH_SCR

Value:

( \

UART_SCR_DMA_MODE_CTL_DMA_MODE_CTL_VALUE_1)

◆ UART_INT_CTS

#define UART_INT_CTS (UART_IER_CTS_IT_MASK)

Values for enabling/disabling the interrupts of UART.

◆ UART_INT_RTS

#define UART_INT_RTS (UART_IER_RTS_IT_MASK)

◆ UART_INT_XOFF

#define UART_INT_XOFF (UART_IER_XOFF_IT_MASK)

◆ UART_INT_SLEEPMODE

#define UART_INT_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)

◆ UART_INT_MODEM_STAT

#define UART_INT_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)

◆ UART_INT_LINE_STAT

#define UART_INT_LINE_STAT (UART_IER_LINE_STS_IT_MASK)

◆ UART_INT_THR

#define UART_INT_THR (UART_IER_THR_IT_MASK)

◆ UART_INT_RHR_CTI

#define UART_INT_RHR_CTI (UART_IER_RHR_IT_MASK)

◆ UART_INT2_RX_EMPTY

#define UART_INT2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)

◆ UART_INT2_TX_EMPTY

#define UART_INT2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)

◆ UART_FIFO_PE_FE_BI_DETECTED

#define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)

Values pertaining to UART Line Status information.

◆ UART_BREAK_DETECTED_ERROR

#define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)

◆ UART_FRAMING_ERROR

#define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)

◆ UART_PARITY_ERROR

#define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)

◆ UART_OVERRUN_ERROR

#define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)

◆ UART_INTID_MODEM_STAT

#define UART_INTID_MODEM_STAT

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

Values pertaining to status of UART Interrupt sources.

◆ UART_INTID_TX_THRES_REACH

#define UART_INTID_TX_THRES_REACH

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INTID_RX_THRES_REACH

#define UART_INTID_RX_THRES_REACH

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INTID_RX_LINE_STAT_ERROR

#define UART_INTID_RX_LINE_STAT_ERROR

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INTID_CHAR_TIMEOUT

#define UART_INTID_CHAR_TIMEOUT

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INTID_XOFF_SPEC_CHAR_DETECT

#define UART_INTID_XOFF_SPEC_CHAR_DETECT

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
                                             <<                               \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INTID_MODEM_SIG_STATE_CHANGE

#define UART_INTID_MODEM_SIG_STATE_CHANGE

Value:

(UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
                                             <<                                \
                                             UART_IIR_IT_TYPE_SHIFT)

◆ UART_INT_PENDING

#define UART_INT_PENDING (0U)

Values indicating the UART Interrupt pending status.

◆ UART_N0_INT_PENDING

#define UART_N0_INT_PENDING (1U)

◆ UART_AUTO_CTS_ENABLE

#define UART_AUTO_CTS_ENABLE

Value:

((uint32_t) (                                    \
                                                 UART_EFR_AUTO_CTS_EN_AUTO_CTS_EN_U_VALUE_1) \
                                             <<                                              \
                                             (UART_EFR_AUTO_CTS_EN_SHIFT))

Values for controlling Auto-CTS and Auto-RTS features.

◆ UART_AUTO_CTS_DISABLE

#define UART_AUTO_CTS_DISABLE

Value:

((uint32_t) (                                    \
                                                 UART_EFR_AUTO_CTS_EN_AUTO_CTS_EN_U_VALUE_0) \
                                             <<                                              \
                                             (UART_EFR_AUTO_CTS_EN_SHIFT))

◆ UART_AUTO_RTS_ENABLE

#define UART_AUTO_RTS_ENABLE

Value:

((uint32_t) (                                    \
                                                 UART_EFR_AUTO_RTS_EN_AUTO_RTS_EN_U_VALUE_1) \
                                             <<                                              \
                                             (UART_EFR_AUTO_RTS_EN_SHIFT))

◆ UART_AUTO_RTS_DISABLE

#define UART_AUTO_RTS_DISABLE

Value:

((uint32_t) (                                    \
                                                 UART_EFR_AUTO_RTS_EN_AUTO_RTS_EN_U_VALUE_0) \
                                             <<                                              \
                                             (UART_EFR_AUTO_RTS_EN_SHIFT))

◆ UART_SPECIAL_CHAR_DETECT_ENABLE

#define UART_SPECIAL_CHAR_DETECT_ENABLE (UART_EFR_SPECIAL_CHAR_DETECT_MASK)

Values to enable/disable detection of Special Character.

◆ UART_SPECIAL_CHAR_DETECT_DISABLE

#define UART_SPECIAL_CHAR_DETECT_DISABLE

Value:

( \

UART_EFR_SPECIAL_CHAR_DETECT_SPECIAL_CHAR_DETECT_U_VALUE_0)

◆ UART_NO_SOFTWARE_FLOW_CONTROL

#define UART_NO_SOFTWARE_FLOW_CONTROL

Value:

((                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_0 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_TX_SHIFT)                 \
                                             |                                                      \
                                             (                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_0 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))

Values to configure the options for Software Flow Control.

◆ UART_TX_RX_XON1_XOFF1

#define UART_TX_RX_XON1_XOFF1

Value:

((                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_2 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_TX_SHIFT)                 \
                                             |                                                      \
                                             (                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_2 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))

◆ UART_TX_RX_XON2_XOFF2

#define UART_TX_RX_XON2_XOFF2

Value:

((                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_1 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_TX_SHIFT)                 \
                                             |                                                      \
                                             (                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_1 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))

◆ UART_TX_RX_XON1_XOFF1_XON2_XOFF2

#define UART_TX_RX_XON1_XOFF1_XON2_XOFF2

Value:

((                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_3 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_TX_SHIFT)                 \
                                             |                                                      \
                                             (                                                      \
                                                 UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_3 \
                                                 <<                                                 \
                                                 UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))

◆ UART_NO_HARDWARE_FLOW_CONTROL

#define UART_NO_HARDWARE_FLOW_CONTROL UART_EFR_HW_NO_FLOW_CONTROL_VALUE

◆ UART_RTS_ENABLE

#define UART_RTS_ENABLE UART_EFR_HW_ENABLE_RTS_VALUE

◆ UART_CTS_ENABLE

#define UART_CTS_ENABLE UART_EFR_HW_ENALE_CTS_VALUE

◆ UART_RTS_CTS_ENABLE

#define UART_RTS_CTS_ENABLE UART_EFR_HW_ENABLE_RTS_CTS_FLOW_CONTROL_VALUE

◆ UART_PULSE_NORMAL

#define UART_PULSE_NORMAL

Value:

(      \
        UART_MDR2_UART_PULSE_UART_PULSE_VALUE_0 << \
        UART_MDR2_UART_PULSE_SHIFT)

Values to enable/disable Pulse shaping for UART.

◆ UART_PULSE_SHAPING

#define UART_PULSE_SHAPING

Value:

(      \
        UART_MDR2_UART_PULSE_UART_PULSE_VALUE_1 << \
        UART_MDR2_UART_PULSE_SHIFT)

◆ UART_TX_DMA_THRESHOLD_64

#define UART_TX_DMA_THRESHOLD_64

Value:

(UART_MDR3_SET_DMA_TX_THRESHOLD_64 \
                                             <<                                \
                                             UART_MDR3_SET_DMA_TX_THRESHOLD_SHIFT)

Values used to control the method of setting the TX DMA Threshold value.

◆ UART_TX_DMA_THRESHOLD_REG

#define UART_TX_DMA_THRESHOLD_REG

Value:

(UART_MDR3_SET_DMA_TX_THRESHOLD_REG \
                                             <<                                 \
                                             UART_MDR3_SET_DMA_TX_THRESHOLD_SHIFT)

◆ UART_XON_ANY_ENABLE

#define UART_XON_ANY_ENABLE

Value:

(UART_MCR_XON_EN_XON_EN_VALUE_1 << \

UART_MCR_XON_EN_SHIFT)

UART_MCR_XON_EN_XON_EN_VALUE_1

#define UART_MCR_XON_EN_XON_EN_VALUE_1

Definition: hw_uart.h:272

Values to enable/disable XON any feature.

◆ UART_XON_ANY_DISABLE

#define UART_XON_ANY_DISABLE

Value:

(UART_MCR_XON_EN_XON_EN_VALUE_0 << \

UART_MCR_XON_EN_SHIFT)

UART_MCR_XON_EN_XON_EN_VALUE_0

#define UART_MCR_XON_EN_XON_EN_VALUE_0

Definition: hw_uart.h:273

◆ UART_LOOPBACK_MODE_ENABLE

#define UART_LOOPBACK_MODE_ENABLE

Value:

(       \
        (uint32_t) UART_MCR_LOOPBACK_EN_LOOPBACK_EN_VALUE_1 << \
        UART_MCR_LOOPBACK_EN_SHIFT)

Values to enable/disable Loopback mode of operation.

◆ UART_LOOPBACK_MODE_DISABLE

#define UART_LOOPBACK_MODE_DISABLE

Value:

(       \
        (uint32_t) UART_MCR_LOOPBACK_EN_LOOPBACK_EN_VALUE_0 << \
        UART_MCR_LOOPBACK_EN_SHIFT)

◆ UART_DCD_CONTROL

#define UART_DCD_CONTROL (UART_MCR_CD_STS_CH_MASK)

Macros used to force the Modem Control lines to active/inactive states.

◆ UART_RI_CONTROL

#define UART_RI_CONTROL (UART_MCR_RI_STS_CH_MASK)

◆ UART_RTS_CONTROL

#define UART_RTS_CONTROL (UART_MCR_RTS_MASK)

◆ UART_DTR_CONTROL

#define UART_DTR_CONTROL (UART_MCR_DTR_MASK)

◆ UART_DCD_VALUE

#define UART_DCD_VALUE (UART_MSR_NCD_STS_MASK)

Values that indicate the values on Modem Control lines.

◆ UART_RI_VALUE

#define UART_RI_VALUE (UART_MSR_NRI_STS_MASK)

◆ UART_DSR_VALUE

#define UART_DSR_VALUE (UART_MSR_NDSR_STS_MASK)

◆ UART_CTS_VALUE

#define UART_CTS_VALUE (UART_MSR_NCTS_STS_MASK)

◆ UART_DCD_STS_CHANGED

#define UART_DCD_STS_CHANGED (UART_MSR_DCD_STS_MASK)

Values used to detect the changes in Modem Control lines.

◆ UART_RI_STS_CHANGED

#define UART_RI_STS_CHANGED (UART_MSR_RI_STS_MASK)

◆ UART_DSR_STS_CHANGED

#define UART_DSR_STS_CHANGED (UART_MSR_DSR_STS_MASK)

◆ UART_CTS_STS_CHANGED

#define UART_CTS_STS_CHANGED (UART_MSR_CTS_STS_MASK)

◆ UART_RX_TRIG_LVL_GRAN_1_DISABLE

#define UART_RX_TRIG_LVL_GRAN_1_DISABLE

Value:

(             \
        UART_SCR_RX_TRIG_GRANU1_RX_TRIG_GRANU1_VALUE_0 << \
        UART_SCR_RX_TRIG_GRANU1_SHIFT)

Values used to enable/disable a granularity of 1 for TX and RX FIFO triggerlevels.

◆ UART_RX_TRIG_LVL_GRAN_1_ENABLE

#define UART_RX_TRIG_LVL_GRAN_1_ENABLE

Value:

(             \
        UART_SCR_RX_TRIG_GRANU1_RX_TRIG_GRANU1_VALUE_1 << \
        UART_SCR_RX_TRIG_GRANU1_SHIFT)

◆ UART_TX_TRIG_LVL_GRAN_1_DISABLE

#define UART_TX_TRIG_LVL_GRAN_1_DISABLE

Value:

(             \
        UART_SCR_TX_TRIG_GRANU1_TX_TRIG_GRANU1_VALUE_0 << \
        UART_SCR_TX_TRIG_GRANU1_SHIFT)

◆ UART_TX_FIFO_LVL_GRAN_1_ENABLE

#define UART_TX_FIFO_LVL_GRAN_1_ENABLE

Value:

(             \
        UART_SCR_TX_TRIG_GRANU1_TX_TRIG_GRANU1_VALUE_1 << \
        UART_SCR_TX_TRIG_GRANU1_SHIFT)

◆ UART_DSRn_INT_DISABLE

#define UART_DSRn_INT_DISABLE

Value:

(UART_SCR_DSR_IT_DSR_IT_VALUE_0 << \

UART_SCR_DSR_IT_SHIFT)

UART_SCR_DSR_IT_DSR_IT_VALUE_0

#define UART_SCR_DSR_IT_DSR_IT_VALUE_0

Definition: hw_uart.h:612

Value used to enable/disable DSRn interrupt.

◆ UART_DSRn_INT_ENABLE

#define UART_DSRn_INT_ENABLE

Value:

(UART_SCR_DSR_IT_DSR_IT_VALUE_1 << \

UART_SCR_DSR_IT_SHIFT)

UART_SCR_DSR_IT_DSR_IT_VALUE_1

#define UART_SCR_DSR_IT_DSR_IT_VALUE_1

Definition: hw_uart.h:611

◆ UART_RX_CTS_DSR_WAKEUP_DISABLE

#define UART_RX_CTS_DSR_WAKEUP_DISABLE

Value:

(                                   \
        UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0 << \
        UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT)

Values to control the module Wake-Up rights for RX, CTSn and DSRn pins.

◆ UART_RX_CTS_DSR_WAKEUP_ENABLE

#define UART_RX_CTS_DSR_WAKEUP_ENABLE

Value:

(                                   \
        UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1 << \
        UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT)

◆ UART_THR_INT_NORMAL

#define UART_THR_INT_NORMAL

Value:

(               \
        UART_SCR_TX_EMPTY_CTL_IT_TX_EMPTY_CTL_IT_VALUE_0 << \
        UART_SCR_TX_EMPTY_CTL_IT_SHIFT)

Values to control the THR interrupt modes.

◆ UART_THR_INT_FIFO_TSR_EMPTY

#define UART_THR_INT_FIFO_TSR_EMPTY

Value:

(               \
        UART_SCR_TX_EMPTY_CTL_IT_TX_EMPTY_CTL_IT_VALUE_1 << \
        UART_SCR_TX_EMPTY_CTL_IT_SHIFT)

◆ UART_DMA_CNTR_NO_RESET_FIFO_RESET

#define UART_DMA_CNTR_NO_RESET_FIFO_RESET

Value:

(               \
        UART_SSR_DMA_COUNTER_RST_DMA_COUNTER_RST_VALUE_0 << \
        UART_SSR_DMA_COUNTER_RST_SHIFT)

Values to control the DMA counter reset features.

◆ UART_DMA_CNTR_RESET_FIFO_RESET

#define UART_DMA_CNTR_RESET_FIFO_RESET

Value:

(               \
        UART_SSR_DMA_COUNTER_RST_DMA_COUNTER_RST_VALUE_1 << \
        UART_SSR_DMA_COUNTER_RST_SHIFT)

◆ UART_RX_CTS_DSR_NO_FALL_EDGE

#define UART_RX_CTS_DSR_NO_FALL_EDGE

Value:

(                             \
        UART_SSR_RX_CTS_DSR_WAKE_UP_STS_RX_CTS_DSR_WAKE_UP_STS_VALUE_0 << \
        UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT)

Values indicating the Falling edge status on RX, CTSn and DSRn pins.

◆ UART_RX_CTS_DSR_FALL_EDGE

#define UART_RX_CTS_DSR_FALL_EDGE

Value:

(                             \
        UART_SSR_RX_CTS_DSR_WAKE_UP_STS_RX_CTS_DSR_WAKE_UP_STS_VALUE_1 << \
        UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT)

◆ UART_TX_FIFO_NOT_FULL

#define UART_TX_FIFO_NOT_FULL

Value:

( \

UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)

Values indicating the filled status of TX FIFO.

◆ UART_TX_FIFO_FULL

#define UART_TX_FIFO_FULL

Value:

( \

UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)

◆ UART_SD_PIN_LOW

#define UART_SD_PIN_LOW

Value:

(UART_ACREG_SD_MOD_SD_MOD_VALUE_1 \
                                             <<                               \
                                             UART_ACREG_SD_MOD_SHIFT)

Values to set/clear the SD pin.

◆ UART_SD_PIN_HIGH

#define UART_SD_PIN_HIGH

Value:

(UART_ACREG_SD_MOD_SD_MOD_VALUE_0 \
                                             <<                               \
                                             UART_ACREG_SD_MOD_SHIFT)

◆ UART_IDLEMODE_FORCE_IDLE

#define UART_IDLEMODE_FORCE_IDLE

Value:

(  \
        UART_SYSC_IDLEMODE_IDLEMODE_VALUE_0 << \
        UART_SYSC_IDLEMODE_SHIFT)

Values controlling Power Management Request/Acknowledgement modes.

◆ UART_IDLEMODE_NO_IDLE

#define UART_IDLEMODE_NO_IDLE

Value:

(  \
        UART_SYSC_IDLEMODE_IDLEMODE_VALUE_1 << \
        UART_SYSC_IDLEMODE_SHIFT)

◆ UART_IDLEMODE_SMART_IDLE

#define UART_IDLEMODE_SMART_IDLE

Value:

(  \
        UART_SYSC_IDLEMODE_IDLEMODE_VALUE_2 << \
        UART_SYSC_IDLEMODE_SHIFT)

◆ UART_IDLEMODE_SMART_IDLE_WAKEUP

#define UART_IDLEMODE_SMART_IDLE_WAKEUP

Value:

(  \
        UART_SYSC_IDLEMODE_IDLEMODE_VALUE_3 << \
        UART_SYSC_IDLEMODE_SHIFT)

◆ UART_WAKEUP_ENABLE

#define UART_WAKEUP_ENABLE

Value:

(    \
        UART_SYSC_ENAWAKEUP_ENAWAKEUP_VALUE_1 << \
        UART_SYSC_ENAWAKEUP_SHIFT)

Values enabling/disabling WakeUp capability.

◆ UART_WAKEUP_DISABLE

#define UART_WAKEUP_DISABLE

Value:

(    \
        UART_SYSC_ENAWAKEUP_ENAWAKEUP_VALUE_0 << \
        UART_SYSC_ENAWAKEUP_SHIFT)

◆ UART_AUTO_IDLE_MODE_ENABLE

#define UART_AUTO_IDLE_MODE_ENABLE

Value:

( \

UART_SYSC_AUTOIDLE_AUTOIDLE_VALUE_1)

Values to enable /disable Autoidle mode.

◆ UART_AUTO_IDLE_MODE_DISABLE

#define UART_AUTO_IDLE_MODE_DISABLE

Value:

( \

UART_SYSC_AUTOIDLE_AUTOIDLE_VALUE_0)

◆ UART_WAKEUP_TX_INTERRUPT

#define UART_WAKEUP_TX_INTERRUPT (UART_WER_EVENT_7_TX_WAKEUP_EN_MASK)

Values that enable/disable Wake-Up generation ability for various signals.

◆ UART_WAKEUP_RLS_INTERRUPT

#define UART_WAKEUP_RLS_INTERRUPT

Value:

( \

UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_MASK)

◆ UART_WAKEUP_RHR_INTERRUPT

#define UART_WAKEUP_RHR_INTERRUPT

Value:

( \

UART_WER_EVENT_5_RHR_INTERRUPT_MASK)

◆ UART_WAKEUP_RX_ACTIVITY

#define UART_WAKEUP_RX_ACTIVITY (UART_WER_EVENT_4_RX_ACTIVITY_MASK)

◆ UART_WAKEUP_DCD_ACTIVITY

#define UART_WAKEUP_DCD_ACTIVITY

Value:

( \

UART_WER_EVENT_3_DCD_CD_ACTIVITY_MASK)

◆ UART_WAKEUP_RI_ACTIVITY

#define UART_WAKEUP_RI_ACTIVITY (UART_WER_EVENT_2_RI_ACTIVITY_MASK)

◆ UART_WAKEUP_DSR_ACTIVITY

#define UART_WAKEUP_DSR_ACTIVITY (UART_WER_EVENT_1_DSR_ACTIVITY_MASK)

◆ UART_WAKEUP_CTS_ACTIVITY

#define UART_WAKEUP_CTS_ACTIVITY (UART_WER_EVENT_0_CTS_ACTIVITY_MASK)

◆ UART_AUTOBAUD_NO_PARITY

#define UART_AUTOBAUD_NO_PARITY

Value:

(          \
        UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_0 << \
        UART_UASR_PARITY_TYPE_SHIFT)

Values indicating the parity in UART Autobauding mode.

◆ UART_AUTOBAUD_PARITY_SPACE

#define UART_AUTOBAUD_PARITY_SPACE

Value:

(          \
        UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_1 << \
        UART_UASR_PARITY_TYPE_SHIFT)

◆ UART_AUTOBAUD_EVEN_PARITY

#define UART_AUTOBAUD_EVEN_PARITY

Value:

(          \
        UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_2 << \
        UART_UASR_PARITY_TYPE_SHIFT)

◆ UART_AUTOBAUD_ODD_PARITY

#define UART_AUTOBAUD_ODD_PARITY

Value:

(          \
        UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_3 << \
        UART_UASR_PARITY_TYPE_SHIFT)

◆ UART_AUTOBAUD_CHAR_LENGTH_7

#define UART_AUTOBAUD_CHAR_LENGTH_7

Value:

(          \
        UART_UASR_BIT_BY_CHAR_BIT_BY_CHAR_U_VALUE_0 << \
        UART_UASR_BIT_BY_CHAR_SHIFT)

Values indicating the word length in UART Autobaud mode.

◆ UART_AUTOBAUD_CHAR_LENGTH_8

#define UART_AUTOBAUD_CHAR_LENGTH_8

Value:

(          \
        UART_UASR_BIT_BY_CHAR_BIT_BY_CHAR_U_VALUE_1 << \
        UART_UASR_BIT_BY_CHAR_SHIFT)

◆ UART_AUTOBAUD_NO_SPEED_IDEN

#define UART_AUTOBAUD_NO_SPEED_IDEN (UART_UASR_SPEED_SPEED_VALUE_0)

Values indicating the baud rate in UART Autobaud mode.

◆ UART_AUTOBAUD_SPEED_115200

#define UART_AUTOBAUD_SPEED_115200 (UART_UASR_SPEED_SPEED_VALUE_1)

◆ UART_AUTOBAUD_SPEED_57600

#define UART_AUTOBAUD_SPEED_57600 (UART_UASR_SPEED_SPEED_VALUE_2)

◆ UART_AUTOBAUD_SPEED_38400

#define UART_AUTOBAUD_SPEED_38400 (UART_UASR_SPEED_SPEED_VALUE_3)

◆ UART_AUTOBAUD_SPEED_28800

#define UART_AUTOBAUD_SPEED_28800 (UART_UASR_SPEED_SPEED_VALUE_4)

◆ UART_AUTOBAUD_SPEED_19200

#define UART_AUTOBAUD_SPEED_19200 (UART_UASR_SPEED_SPEED_VALUE_5)

◆ UART_AUTOBAUD_SPEED_14400

#define UART_AUTOBAUD_SPEED_14400 (UART_UASR_SPEED_SPEED_VALUE_6)

◆ UART_AUTOBAUD_SPEED_9600

#define UART_AUTOBAUD_SPEED_9600 (UART_UASR_SPEED_SPEED_VALUE_7)

◆ UART_AUTOBAUD_SPEED_4800

#define UART_AUTOBAUD_SPEED_4800 (UART_UASR_SPEED_SPEED_VALUE_8)

◆ UART_AUTOBAUD_SPEED_2400

#define UART_AUTOBAUD_SPEED_2400 (UART_UASR_SPEED_SPEED_VALUE_9)

◆ UART_AUTOBAUD_SPEED_1200

#define UART_AUTOBAUD_SPEED_1200 (UART_UASR_SPEED_SPEED_VALUE_10)

◆ UART_TRIG_LVL_GRANULARITY_4

#define UART_TRIG_LVL_GRANULARITY_4 ((uint32_t) 0x0000U)

Values used to choose the trigger level granularity.

◆ UART_TRIG_LVL_GRANULARITY_1

#define UART_TRIG_LVL_GRANULARITY_1 ((uint32_t) 0x0001U)

◆ UART_REG_CONFIG_MODE_A

#define UART_REG_CONFIG_MODE_A (uint32_t) (0x0080)

Values to be used while switching between register configuration modes.

◆ UART_REG_CONFIG_MODE_B

#define UART_REG_CONFIG_MODE_B (uint32_t) (0x00BF)

◆ UART_REG_OPERATIONAL_MODE

#define UART_REG_OPERATIONAL_MODE (uint32_t) (0x007F)

◆ UART_FIFO_CONFIG

#define UART_FIFO_CONFIG	(	txGra,
		rxGra,
		txTrig,
		rxTrig,
		txClr,
		rxClr,
		dmaEnPath,
		dmaMode
	)

Value:

(((uint32_t) (txGra & 0xFU) << (uint32_t)26U)    |                       \
     ((uint32_t) (rxGra & 0xFU) << (uint32_t)22U)    |                       \
     ((uint32_t) (txTrig & 0xFFU) << (uint32_t)14U)  |                       \
     ((uint32_t) (rxTrig & 0xFFU) << (uint32_t)6U)   |                       \
     ((uint32_t) (txClr & 0x1U) << (uint32_t)5U)     |                       \
     ((uint32_t) (rxClr & 0x1U) << (uint32_t)4U)     |                       \
     ((uint32_t) (dmaEnPath & 0x1U) << (uint32_t)3U) |                       \
     (uint32_t) (dmaMode & 0x7U))

Parameterized macro to configure the FIFO settings.

◆ UART_FCR_PROGRAM

#define UART_FCR_PROGRAM	(	rxFIFOTrig,
		txFIFOTrig,
		dmaMode,
		txClr,
		rxClr,
		fifoEn
	)

Value:

(((uint32_t) (((uint32_t) (rxFIFOTrig) & 0x3U) << 6)) |                     \
     ((uint32_t) (((uint32_t) (txFIFOTrig) & 0x3U) << 4)) |                     \
     (((uint32_t))(((uint32_t) (dmaMode) & 0x1U) << 3)) |                       \
     (((uint32_t))(((uint32_t) (txClr) & 0x1U) << 2)) |                         \
     ((uint32_t) (((uint32_t) (rxClr) & 0x1U) << 1)) |                          \
     ((uint32_t) (fifoEn) & 0x1U))

Parameterized macro used to determine a value to be written to FCR.

◆ UART_FIFO_CONFIG_TXGRA

#define UART_FIFO_CONFIG_TXGRA ((uint32_t) 0xFU << 26)

◆ UART_FIFO_CONFIG_RXGRA

#define UART_FIFO_CONFIG_RXGRA ((uint32_t) 0xFU << 22)

◆ UART_FIFO_CONFIG_TXTRIG

#define UART_FIFO_CONFIG_TXTRIG ((uint32_t) 0xFFU << 14)

◆ UART_FIFO_CONFIG_RXTRIG

#define UART_FIFO_CONFIG_RXTRIG ((uint32_t) 0xFFU << 6)

◆ UART_FIFO_CONFIG_TXCLR

#define UART_FIFO_CONFIG_TXCLR ((uint32_t) 0x1U << 5)

◆ UART_FIFO_CONFIG_RXCLR

#define UART_FIFO_CONFIG_RXCLR ((uint32_t) 0x1U << 4)

◆ UART_FIFO_CONFIG_DMAENPATH

#define UART_FIFO_CONFIG_DMAENPATH ((uint32_t) 0x1U << 3)

◆ UART_FIFO_CONFIG_DMAMODE

#define UART_FIFO_CONFIG_DMAMODE ((uint32_t) 0x7U << 0)

◆ UART_MIR_OVERSAMPLING_RATE_41

#define UART_MIR_OVERSAMPLING_RATE_41 ((uint32_t) 41U)

Over-sampling rate for MIR mode used to obtain the Divisor Values.

◆ UART_MIR_OVERSAMPLING_RATE_42

#define UART_MIR_OVERSAMPLING_RATE_42 ((uint32_t) 42U)

◆ UART_FCR_TX_FIFO_TRIG_8SPACES

#define UART_FCR_TX_FIFO_TRIG_8SPACES ((uint32_t) 0x0U)

◆ UART_FCR_TX_FIFO_TRIG_16SPACES

#define UART_FCR_TX_FIFO_TRIG_16SPACES ((uint32_t) 0x1U)

◆ UART_FCR_TX_FIFO_TRIG_32SPACES

#define UART_FCR_TX_FIFO_TRIG_32SPACES ((uint32_t) 0x2U)

◆ UART_FCR_TX_FIFO_TRIG_56SPACES

#define UART_FCR_TX_FIFO_TRIG_56SPACES ((uint32_t) 0x3U)

◆ UART_LCR_STB_SHIFT

#define UART_LCR_STB_SHIFT ((uint32_t) 0x00000002U)

used in uart console init function

◆ UART_LCR_PEN_SHIFT

#define UART_LCR_PEN_SHIFT ((uint32_t) 0x00000003U)

◆ UART_LCR_BC_SHIFT

#define UART_LCR_BC_SHIFT ((uint32_t) 0x00000006U)

◆ UART_LCR_PARITY_EN_DISABLE

#define UART_LCR_PARITY_EN_DISABLE ((uint32_t) 0x0U)

◆ UART_MDR1_MODE_SELECT_CIR

#define UART_MDR1_MODE_SELECT_CIR ((uint32_t) 0x6U)

◆ UART_MDR1_MODE_SELECT_DISABLED

#define UART_MDR1_MODE_SELECT_DISABLED ((uint32_t) 0x7U)

◆ UART_MDR1_MODE_SELECT_FIR

#define UART_MDR1_MODE_SELECT_FIR ((uint32_t) 0x5U)

◆ UART_MDR1_MODE_SELECT_MIR

#define UART_MDR1_MODE_SELECT_MIR ((uint32_t) 0x4U)

◆ UART_MDR1_MODE_SELECT_SIR

#define UART_MDR1_MODE_SELECT_SIR ((uint32_t) 0x1U)

◆ UART_MDR1_MODE_SELECT_UART13X

#define UART_MDR1_MODE_SELECT_UART13X ((uint32_t) 0x3U)

◆ UART_MDR1_MODE_SELECT_UART16X

#define UART_MDR1_MODE_SELECT_UART16X ((uint32_t) 0x0U)

◆ UART_MDR1_MODE_SELECT_UART16XAUTO

#define UART_MDR1_MODE_SELECT_UART16XAUTO ((uint32_t) 0x2U)

◆ UART_FCR_RX_FIFO_TRIG_16CHAR

#define UART_FCR_RX_FIFO_TRIG_16CHAR ((uint32_t) 0x1U)

◆ UART_FCR_RX_FIFO_TRIG_56CHAR

#define UART_FCR_RX_FIFO_TRIG_56CHAR ((uint32_t) 0x2U)

◆ UART_FCR_RX_FIFO_TRIG_60CHAR

#define UART_FCR_RX_FIFO_TRIG_60CHAR ((uint32_t) 0x3U)

◆ UART_FCR_RX_FIFO_TRIG_8CHAR

#define UART_FCR_RX_FIFO_TRIG_8CHAR ((uint32_t) 0x0U)

◆ UART_EFR_SW_FLOW_CONTROL_RX_SHIFT

#define UART_EFR_SW_FLOW_CONTROL_RX_SHIFT ((uint32_t) 0x0U)

◆ UART_EFR_SW_FLOW_CONTROL_TX_SHIFT

#define UART_EFR_SW_FLOW_CONTROL_TX_SHIFT ((uint32_t) 0x2U)

◆ UART_MDR3_SET_DMA_TX_THRESHOLD_64

#define UART_MDR3_SET_DMA_TX_THRESHOLD_64 ((uint32_t) 0x0U)

macros used to determine a value to be written to MDR3.

◆ UART_MDR3_SET_DMA_TX_THRESHOLD_REG

#define UART_MDR3_SET_DMA_TX_THRESHOLD_REG ((uint32_t) 0x1U)

◆ UART_MDR3_DIR_POL_0

#define UART_MDR3_DIR_POL_0 ((uint32_t) 0U)

◆ UART_MDR3_DIR_POL_1

#define UART_MDR3_DIR_POL_1 ((uint32_t) 1U)

Function Documentation

◆ UARTOperatingModeSelect()

uint32_t UARTOperatingModeSelect	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API configures the operating mode for the UART instance. The different operating modes are:

UART(16x, 13x, 16x Auto-Baud)
IrDA(SIR, MIR, FIR)
CIR
Disabled state(default state)

Parameters

baseAddr Memory address of the UART instance being used.

modeFlag A value which holds the mode number. This mode number is referred from the MODESELECT field in MDR1.

'modeFlag' can take one of the following values: UART16x_OPER_MODE : to switch to UART 16x operating mode
UART_SIR_OPER_MODE : to swith to IrDA SIR operating mode
UART16x_AUTO_BAUD_OPER_MODE : to switch to UART 16x Auto Baud operating mode
UART13x_OPER_MODE : to switch to UART 13x operating mode
UART_MIR_OPER_MODE : to switch to IrDA MIR operating mode
UART_FIR_OPER_MODE : to switch to IrDA FIR operating mode
UART_CIR_OPER_MODE : to switch to CIR operating mode
UART_DISABLED_MODE : to switch to Disabled state

Returns
The mode number in the MODESELECT field of MDR1 before it was modified.

◆ UARTDivisorValCompute()

uint32_t UARTDivisorValCompute	(	uint32_t	moduleClk,
		uint32_t	baudRate,
		uint32_t	modeFlag,
		uint32_t	mirOverSampRate
	)

This API computes the divisor value for the specified operating mode. Not part of this API, the divisor value returned is written to the Divisor Latches to configure the Baud Rate.

Parameters

moduleClk	The frequency of the input clock to the UART module
modeFlag	A value which represents the current operating mode
baudRate	The required baud rate of communication in bits per second(bps)
mirOverSampRate	Over-sampling rate for MIR mode.This is applicable only when MIR mode of operation is chosen. Otherwise, this value is not considered.

'modeFlag' can take one of the following values:

UART16x_OPER_MODE - indicating 16x operating mode
UART13x_OPER_MODE - indicating 13x operating mode
UART_SIR_OPER_MODE - indicating SIR operating mode
UART_MIR_OPER_MODE - indicating MIR operating mode
UART_FIR_OPER_MODE - indicating FIR operating mode
'mirOverSampRate' can take one of the following values:
UART_MIR_OVERSAMPLING_RATE_41 - for an over-sampling rate of 41
UART_MIR_OVERSAMPLING_RATE_42 - for an over-smapling rate of 42

Returns
The divisor value computed for the specified mode.

Note
Refer to the section in the user guide that specifies the baud rate computation method to find the supported values of baud rates.

◆ UARTDivisorLatchWrite()

uint32_t UARTDivisorLatchWrite	(	uint32_t	baseAddr,
		uint32_t	divisorValue
	)

This API is used to write the specified divisor value to Divisor Latch registers DLL and DLH.

Parameters

baseAddr	Memory address of the UART instance being used.
divisorValue	The 14-bit value whose least 8 bits go to DLL and highest 6 bits go to DLH.

Returns: A concatenated value of DLH and DLL registers(DLH:DLL, a 14-bit value) before they are modified in the current API.

◆ UARTDivisorLatchEnable()

void UARTDivisorLatchEnable ( uint32_t baseAddr )

This API enables write access to Divisor Latch registers DLL and DLH.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: None.

◆ UARTDivisorLatchDisable()

void UARTDivisorLatchDisable ( uint32_t baseAddr )

This API disables write access to Divisor Latch registers DLL and DLH.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: None.

Note: Disabling write access to Divisor Latch Registers enables access to MCR, FCR, IER, BLR, EBLR, RHR registers.

◆ UARTRegConfigModeEnable()

uint32_t UARTRegConfigModeEnable	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API configures the specified Register Configuration mode for the UART.

Parameters

baseAddr	Memory address of the UART instance being used.
modeFlag	This specifies the register configuration mode to be enabled.

Returns: The contents of the Line Control Register(LCR) before it was modified.

Note

Since the UART module registers that can be accessed at any time depends on the value in the Line Control Register(LCR), three register configuration modes have been defined, each corresponding to a specific state of the LCR. The three register configuration modes are:

Configuration Mode A: LCR[7] = 1 and LCR[7:0] != 0xBF.
Configuration Mode B: LCR[7:0] = 0xBF.
Operational Mode : LCR[7] = 0.
Refer to the Register Listing in the UART/IrDA/CIR peripheral document for more information.

◆ UARTRegConfModeRestore()

void UARTRegConfModeRestore	(	uint32_t	baseAddr,
		uint32_t	lcrRegValue
	)

This API is used to restore the UART to the specified Register Configuration Mode.

Parameters

baseAddr	Memory address of the UART instance being used.
lcrRegValue	The value to be loaded to the Line Control Register(LCR).

Returns: None

Note: The API UARTRegConfigModeEnable() and the current API are used hand-in-hand. While UARTRegConfigModeEnable() switches the UART to the requested operating mode, the current API restores the UART to that register configuration mode prevalent before UARTRegConfigModeEnable() was called.

◆ UARTBreakCtl()

void UARTBreakCtl	(	uint32_t	baseAddr,
		uint32_t	breakState
	)

This API is used to introduce or to remove a Break condition.

Parameters

baseAddr	Memory address of the UART instance being used.
breakState	This specifies whether the break condition should be introduced or removed.

'breakState' can take one of the following two values:

UART_BREAK_COND_DISABLE - to disable the Break condition if it has already been enabled
UART_BREAK_COND_ENABLE - to enable the Break condition

Returns
None

Note
When the Break Condition is imposed, the Transmitter output line TX goes low to alert the communication terminal.

◆ UARTLineCharacConfig()

void UARTLineCharacConfig	(	uint32_t	baseAddr,
		uint32_t	wLenStbFlag,
		uint32_t	parityFlag
	)

This API configures the Line Characteristics for the UART instance. The Line Characteristics include:

Word length per frame
Number of Stop Bits per frame

Parity feature configuration

Parameters

baseAddr	Memory address of the UART instance being used.
wLenStbFlag	Bit mask value of the bits pertaining to word length selection and stop bits selection in LCR.
parityFlag	Bit mask value of the bits pertaining to parity feature selection in LCR.

'wLenStbFlag' can take one of the following macros: – (UART_FRAME_WORD_LENGTH_n | UART_FRAME_NUM_STB_1), where n = 5,6,7 or 8. – This signifies that 1 stop bit and one among 5,6,7 and 8 bits are chosen as the word length per frame.
– (UART_FRAME_WORD_LENGTH_n | UART_FRAME_NUM_STB_1_5_2), where n = 5,6,7 or 8. – This signifies that the word length and number of stop bits per frame could be one among the below four choices: — WL = 5 NUM_STB = 1.5 — WL = 6,7 or 8 NUM_STB = 2

'parityFlag' can take one of the following macros:

(UART_ODD_PARITY) - signifying that odd parity be enabled and the parity bit be represented in a default manner.
(UART_EVEN_PARITY) - signifying that even parity be enabled and the parity bit be represented in a default manner.
(UART_PARITY_REPR_1) - signifying that the parity bit be represented by a logic 1 in the transmitted and received data.
(UART_PARITY_REPR_0) - signifying that the parity bit be represented by a logic 0 in the transmitted and received data.
(UART_PARITY_NONE) - signifying that no parity be enabled.

Returns
None.

◆ UARTParityModeSet()

void UARTParityModeSet	(	uint32_t	baseAddr,
		uint32_t	parityFlag
	)

This API configures the Parity feature for the UART.

Parameters

baseAddr	Memory address of the UART instance being used
parityFlag	This specifies the parity configuration to be programmed to the Line Control Register(LCR)

'parityFlag' can take one of the following values:

(UART_ODD_PARITY) - signifying that odd parity be enabled and the parity bit be represented in a default manner
(UART_EVEN_PARITY) - signifying that even parity be enabled and the parity bit be represented in a default manner
(UART_ODD_PARITY_REPR_1) - signifying that odd parity be enabled and the parity bit be represented by a logic 1
(UART_EVEN_PARITY_REPR_0)- signifying that even parity be enabled and the parity bit be represented by a logic 0
(UART_PARITY_NONE) - signifying that no parity be enabled

Returns
None

◆ UARTParityModeGet()

uint32_t UARTParityModeGet ( uint32_t baseAddr )

This API reads the Parity configuration being set in the UART.

Parameters

baseAddr Memory address of the UART instance being used

Returns

This returs one of the following values:

(UART_ODD_PARITY) - signifying that odd parity is enabled and the parity bit is represented in a default manner
(UART_EVEN_PARITY) - signifying that even parity is enabled and the parity bit is represented in a default manner
(UART_ODD_PARITY_REPR_1) - signifying that odd parity is enabled and the parity bit is represented by a logic 1
(UART_EVEN_PARITY_REPR_0)- signifying that even parity is enabled and the parity bit is represented by a logic 0
(UART_PARITY_NONE) - signifying that no parity is enabled

◆ UARTDMAEnable()

void UARTDMAEnable	(	uint32_t	baseAddr,
		uint32_t	dmaModeFlag
	)

This API enables the DMA mode of operation for the UART instance.

Parameters

baseAddr	Memory address of the UART instance being used.
dmaModeFlag	This specifies the DMA mode to be enabled for the UART instance.

'dmaModeFlag' can take one of the following four values:

UART_DMA_MODE_0_ENABLE - to enable DMA Mode 0(No DMA)
UART_DMA_MODE_1_ENABLE - to enable DMA Mode 1(DMA for both TX and RX)
UART_DMA_MODE_2_ENABLE - to enable DMA Mode 2(DMA only for RX)
UART_DMA_MODE_3_ENABLE - to enable DMA Mode 3(DMA only for TX)

Returns
None

Note
This API enables the specified DMA modes always in SCR and FCR is not used. This is because SCR[2:1] allows the program to enable any of the four available DMA modes while FCR[3] allows the program to use either DMA Mode 0 or DMA Mode 1.

◆ UARTDMADisable()

void UARTDMADisable ( uint32_t baseAddr )

This API disables the DMA mode of operation.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: None

◆ UARTFIFOConfig()

uint32_t UARTFIFOConfig	(	uint32_t	baseAddr,
		uint32_t	fifoConfig
	)

This API configures the FIFO settings for the UART instance. Specifically, this does the following configurations: 1> Configures the Transmitter and Receiver FIFO Trigger Level granularity
2> Configures the Transmitter and Receiver FIFO Trigger Level
3> Configures the bits which clear/not clear the TX and RX FIFOs
4> Configures the DMA mode of operation
.

Parameters

baseAddr	Memory address of the UART instance being used.
fifoConfig	This specifies the desired FIFO configurations. Use the macro UART_FIFO_CONFIG to pass the required FIFO settings.

The parameters of UART_FIFO_CONFIG can take the following values:
– txGra - the Transmitter FIFO trigger level granularity
– rxGra - the Receiver FIFO trigger level granularity
These can take one of the following two values:

UART_TRIG_LVL_GRANULARITY_1 - for a granularity of 1,
UART_TRIG_LVL_GRANULARITY_4 - for a granularity of 4.
– txTrig - the Transmitter FIFO trigger level
For 'txGra' being UART_TRIG_LVL_GRANULARITY_4, this can take one of the values from one of the following two sets: Set 1> UART_FCR_TX_TRIG_LVL_n, where n = 8,16,32,56. These are programmed to the FCR[5:4] in FCR register. Set 2> m , where (1 <= m <= 15). The trigger level would then be (m * 4). For example: If m = 9, then trigger level = 36. The value 'm' is programmed into TLR[3:0] field in TLR register.

For granularity being UART_TRIG_LVL_GRANULARITY_1, this can take any decimal value from 1 to 63.

– rxTrig - the Receiver FIFO Trigger level
For granularity being UART_TRIG_LVL_GRANULARITY_4, this can take one of the macro from one of the following two sets: Set 1> UART_FCR_RX_TRIG_LVL_n, where n = 8,16,56,60. These are programmed into FCR[7:6] field in FCR register. Set 2> m , where (1 <= m <= 15). The trigger level would then be (m * 4). For example: If m = 7, then trigger level = 28. The value 'm' is programmed to the TLR[7:4] field of TLR.

For granularity being UART_TRIG_LVL_GRANULARITY_1, this can take any decimal value from 1 to 63.

– txClr - the Transmitter FIFO clear flag
– rxClr - the Receiver FIFO clear flag
These can take the following values: 0 - to not clear the FIFO
1 - to clear the FIFO. Clearing the FIFO also results in resetting the FIFO counter logic to 0.
– dmaEnPath - specifies whether DMA Mode settings should be configured through FCR or SCR. This can take one of the following two values: UART_DMA_EN_PATH_FCR - to configure DMA through FCR
UART_DMA_EN_PATH_SCR - to configure DMA through SCR
– dmaMode - specifies the DMA Mode to be used
This can take one of the following four values:

UART_DMA_MODE_m_ENABLE, where m = 0, 1, 2 or 3.

Returns: The value that was written to the FIFO Control Register(FCR).

Note: 1> FIFO Control Register(FCR) is a write-only register and its contents cannot be read. Hence, it is not possible for a read-modify-write operation on this register. Therefore it is expected that the FIFO configuration is done at once for both TX and RX directions and always the entire FCR related information is required during modification of the FIFO settings. Also the FIFO related settings are valid only when the FIFO is enabled. This means that FIFO mode of operation should be enabled for FIFO related settings to take effect.

◆ UARTEnhanFuncEnable()

uint32_t UARTEnhanFuncEnable ( uint32_t baseAddr )

This API sets a certain bit in Enhanced Feature Register(EFR) which shall avail the UART to use some Enhanced Features.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The value of ENHANCEDEN bit in EFR before it is modified in this API.

Note: This API switches UART to Configuration Mode B, sets the ENHANCEDEN bit in EFR and reverts the UART back to the original mode of operation.

◆ UARTEnhanFuncBitValRestore()

void UARTEnhanFuncBitValRestore	(	uint32_t	baseAddr,
		uint32_t	enhanFnBitVal
	)

This API restores the ENHANCEDEN bit value of EFR register(EFR[4]) to the corresponding bit value in 'enhanFnBitVal' passed as a parameter to this API.

Parameters

baseAddr	Memory address of the UART instance being used.
enhanFnBitVal	The 4th bit of this 32-bit value shall hold a value to which the ENHANCEDEN bit of EFR (EFR[4]) has to be restored to.

Returns: None.

Note: The APIs UARTEnhanFuncEnable() and the current one are used hand-in-hand. While UARTEnhanFuncEnable() collects the EFR[4] bit value before modifying it, UARTEnhanFuncBitValRestore() can be used to restore EFR[4] bit value after the necessary operation is complete. This API switches the UART to Configuration Mode B, does the needful and reverts it back to original mode of operation.

◆ UARTSubConfigMSRSPRModeEn()

uint32_t UARTSubConfigMSRSPRModeEn ( uint32_t baseAddr )

This API enables the MSR_SPR Sub-Configuration Mode of operation.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The value of the TCRTLR bit in MCR (MCR[6]) before it is modified in this API.

Note: 1> Each Register configuration mode(A, B and operational) has further sub-configuration modes corresponding to accesses to offset addresses 0x18 and 0x1C. They are:
For Register Configuration Mode A:
1> MSR_SPR: EFR[4] = 0 or MCR[6] = 0
2> TCR_TLR: EFR[4] = 1 and MCR[6] = 1
For Register Configuration Mode B:
1> TCR_TLR - EFR[4] = 1 and MCR[6] = 1
2> XOFF - EFR[4] = 0 or MCR[6] = 0
For Register Operational Mode:
1> MSR_SPR - EFR[4] = 0 or MCR[6] = 0
2> TCR_TLR - EFR[4] = 1 and MCR[6] = 1
In any configuration mode, enabling one of the sub-configuration mode would disable access to the registers of the other sub-configuration mode.
2> The current API enables access to Modem Status Register(MSR) and Scratch Pad Register(SPR). This is applicable for Register Configuration Mode A and Operational mode of operation.

◆ UARTSubConfigTCRTLRModeEn()

uint32_t UARTSubConfigTCRTLRModeEn ( uint32_t baseAddr )

This API enables the TCR_TLR Sub_Configuration Mode of operation.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The value of the TCRTLR bit in MCR (MCR[6]) before it is modified in this API.

Note: The current API enables access to Transmission Control Register(TCR) and Trigger Level Register(TLR). This is applicable for all the three register configuration modes. Refer to the comments of UARTSubConfigMSRSPRModeEn() API for more details.

◆ UARTSubConfigXOFFModeEn()

uint32_t UARTSubConfigXOFFModeEn ( uint32_t baseAddr )

This API enables the XOFF Sub-Configuration Mode of operation.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The value of the TCRTLR bit in MCR (MCR[6]) before it is modified in this API.

Note: The current API enables access to the XOFF (XOFF1 and XOFF2) registers. The XOFF registers can be accessed in Register Configuration Mode B of operation. Refer to the comments of UARTSubConfigMSRSPRModeEn() API for more details.

◆ UARTTCRTLRBitValRestore()

void UARTTCRTLRBitValRestore	(	uint32_t	baseAddr,
		uint32_t	tcrTlrBitVal
	)

This API restores the TCRTLR bit(MCR[6]) value in Modem Control Register(MCR) to the corresponding bit value in 'tcrTlrBitVal' passed as a parameter to this API.

Parameters

baseAddr	Memory address of the UART instance being used.
tcrTlrBitVal	The 6th bit in this 32-bit value shall hold a value to which the TCRTLR bit(MCR[6]) of MCR has to be restored to.

Returns: None.

◆ UARTIntEnable()

void UARTIntEnable	(	uint32_t	baseAddr,
		uint32_t	intFlag
	)

This API enables the specified interrupts in the UART mode of operation.

Parameters

baseAddr	Memory address of the UART instance being used.
intFlag	Bit mask value of the bits corresponding to Interrupt Enable Register(IER). This specifies the UART interrupts to be enabled.

'intFlag' can take one or a combination of the following macros:

UART_INT_CTS - to enable Clear-To-Send interrupt,
UART_INT_RTS - to enable Request-To-Send interrupt,
UART_INT_XOFF - to enable XOFF interrupt,
UART_INT_SLEEPMODE - to enable Sleep Mode,
UART_INT_MODEM_STAT - to enable Modem Status interrupt,
UART_INT_LINE_STAT - to enable Line Status interrupt,
UART_INT_THR - to enable Transmitter Holding Register Empty interrupt,
UART_INT_RHR_CTI - to enable Receiver Data available interrupt and Character timeout indication interrupt.

Returns: None.

Note: This API modifies the contents of UART Interrupt Enable Register (IER). Modifying the bits IER[7:4] requires that EFR[4] be set. This API does the needful before it accesses IER. Moreover, this API should be called when UART is operating in UART 16x Mode, UART 13x Mode or UART 16x Auto-baud mode.

◆ UARTIntDisable()

void UARTIntDisable	(	uint32_t	baseAddr,
		uint32_t	intFlag
	)

This API disables the specified interrupts in the UART mode of operation.

Parameters

baseAddr	Memory address of the UART instance being used.
intFlag	Bit mask value of the bits corresponding to Interrupt Enable Register(IER). This specifies the UART interrupts to be disabled.

'intFlag' can take one or a combination of the following macros:

UART_INT_CTS - to disable Clear-To-Send interrupt,
UART_INT_RTS - to disable Request-To-Send interrupt,
UART_INT_XOFF - to disable XOFF interrupt,
UART_INT_SLEEPMODE - to disable Sleep Mode,
UART_INT_MODEM_STAT - to disable Modem Status interrupt,
UART_INT_LINE_STAT - to disable Line Status interrupt,
UART_INT_THR - to disable Transmitter Holding Register Empty interrupt,
UART_INT_RHR_CTI - to disable Receiver Data available interrupt and Character timeout indication interrupt.

Returns: None

Note: The note section of UARTIntEnable() also applies to this API.

◆ UARTInt2Enable()

void UARTInt2Enable	(	uint32_t	baseAddr,
		uint32_t	intFlag
	)

This API enables the specified interrupts in the UART mode of operation for IER2.

Parameters

baseAddr	Memory address of the UART instance being used.
intFlag	Bit mask value of the bits corresponding to Interrupt Enable Register(IER2). This specifies the UART interrupts to be enabled.

'intFlag' can take one or a combination of the following macros:

UART_INT2_RX_EMPTY - to enable receive FIFO empty interrupt
UART_INT2_TX_EMPTY - to enable TX FIFO empty interrupt

Returns: None.

Note: This API modifies the contents of UART Interrupt Enable Register 2 (IER2).

◆ UARTInt2Disable()

void UARTInt2Disable	(	uint32_t	baseAddr,
		uint32_t	intFlag
	)

This API disables the specified interrupts in the UART mode of operation for IER2.

Parameters

baseAddr	Memory address of the UART instance being used.
intFlag	Bit mask value of the bits corresponding to Interrupt Enable Register(IER2). This specifies the UART interrupts to be disabled.

'intFlag' can take one or a combination of the following macros:

UART_INT2_RX_EMPTY - to enable receive FIFO empty interrupt
UART_INT2_TX_EMPTY - to enable TX FIFO empty interrupt

Returns: None

Note: The note section of UARTInt2Enable() also applies to this API.

◆ UARTSpaceAvail()

uint32_t UARTSpaceAvail ( uint32_t baseAddr )

This API checks whether the TX FIFO (or THR in non-FIFO mode) is empty or not.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: TRUE - if the Transmitter FIFO(or THR in non-FIFO mode) is empty. FALSE - if the Transmitter FIFO(or THR in non-FIFO mode) is not empty.

◆ UARTCharsAvail()

uint32_t UARTCharsAvail ( uint32_t baseAddr )

This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: TRUE - if there is atleast one data byte present in the RX FIFO (or RHR in non-FIFO mode)
FALSE - if there are no data bytes present in the RX FIFO(or RHR in non-FIFO mode)

◆ UARTCharPutNonBlocking()

uint32_t UARTCharPutNonBlocking	(	uint32_t	baseAddr,
		uint8_t	byteWrite
	)

This API attempts to write a byte into Transmitter Holding Register (THR). It checks only once if the transmitter is empty.

Parameters

baseAddr	Memory address of the UART instance being used.
byteWrite	Byte to be written into the THR register.

Returns: TRUE if the transmitter FIFO(or THR register in non-FIFO mode) was empty and the character was written. Else it returns FALSE.

◆ UARTCharGetNonBlocking()

int8_t UARTCharGetNonBlocking ( uint32_t baseAddr )

This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is ready to be read.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: If the RX FIFO(or RHR) was found to have atleast one byte of data, then this API reads and returns that byte. Else it returns -1.

◆ UARTCharGet()

int8_t UARTCharGet ( uint32_t baseAddr )

This API waits indefinitely for the arrival of a byte in the receiver FIFO. Once a byte has arrived, it returns that byte.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: This returns the read byte.

◆ UARTCharGetTimeout()

uint8_t UARTCharGetTimeout	(	uint32_t	baseAddr,
		uint32_t	timeOutVal
	)

This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeout value gets decremented to zero, whichever happens first.

Parameters

baseAddr	Memory address of the UART instance being used.
timeOutVal	The timeout value that is to be used. This timeout value gets decremented once per iteration of the wait loop. wait loop.

Returns: This returns either of the below two values:
1) If a character was keyed in before the timeout value gets decremented to zero, this API returns the entered byte.
2) If no character was input within the timeout value getting decremented to zero, this API returns 0xFF.

◆ UARTCharPut()

void UARTCharPut	(	uint32_t	baseAddr,
		uint8_t	byteTx
	)

This API waits indefinitely until the Transmitter FIFO (THR register in non-FIFO mode) and Transmitter Shift Register are empty. On empty, it writes a byte to the THR.

Parameters

baseAddr	Memory address of the UART instance being used
byteTx	The byte to be transmitted by the UART.

Returns: None

◆ UARTFIFOCharPut()

void UARTFIFOCharPut	(	uint32_t	baseAddr,
		uint8_t	byteTx
	)

This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter FIFO or the Transmitter Shift Register(TSR).

Parameters

baseAddr	Memory address of the UART instance being used.
byteTx	The byte to be transmitted by the UART.

Returns: None

Note: Unlike the APIs UARTCharPut() or UARTCharPutNonBlocking(), this API does not check for the emptiness of the TX FIFO or TSR. This API is ideal for use in FIFO mode of operation where the 64-byte TX FIFO has to be written with successive bytes. If transmit interrupt is enabled, it provides a mechanism to control the writes to the TX FIFO.

◆ UARTFIFOCharGet()

int8_t UARTFIFOCharGet ( uint32_t baseAddr )

This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding Register(RHR). However before reading the data from RHR, it does not check whether RHR has fresh data or not.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The data read from the RHR.

Note: 1) Since this API does not check whether RX FIFO(RHR) has fresh data before reading the same, the application should ensure that RX FIFO has data before calling this API. The API UARTCharsAvail() can be used to check if the RX FIFO has atleast one byte of data.
2) If the RX FIFO did not have any fresh data and this API is called, this API would return an unknown value.

◆ UARTFIFOWrite()

uint32_t UARTFIFOWrite	(	uint32_t	baseAddr,
		const uint8_t *	pBuffer,
		uint32_t	numTxBytes
	)

This API copies the requested amount of data from the pointed data block to the UART Transmit FIFO.

Parameters

baseAddr	Memory address of the UART instance being used.
pBuffer	The starting address of the data block.
numTxBytes	The number of data bytes to be transmitted.

Returns: The number of data bytes that were written to the TX FIFO.

Note: This API does not check for the emptiness of the TX FIFO or for its space availability before writing to it. The application calling this API has the responsibility of checking the TX FIFO status before using this API.

◆ UARTRxErrorGet()

uint32_t UARTRxErrorGet ( uint32_t baseAddr )

This API reads the receiver data error status.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns the error status. This can be one or a combination of the below values:

UART_OVERRUN_ERROR - indicating Overrun error occured
UART_PARITY_ERROR - indicating Parity error occured
UART_FRAMING_ERROR - indicating Framing error occured
UART_BREAK_DETECTED_ERROR - indicating a Break condition was detected
UART_FIFO_PE_FE_BI_DETECTED - indicating that atleast one parity error, framing error or a break indication is present in the RX FIFO

◆ UARTIntIdentityGet()

uint32_t UARTIntIdentityGet ( uint32_t baseAddr )

This API determines the UART Interrupt Status.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one or a combination of the following macros:

UART_INTID_MODEM_STAT - indicating the occurence of a Modem Status interrupt
UART_INTID_TX_THRES_REACH - indicating that the TX FIFO Threshold number of bytes can be written to the TX FIFO.
UART_INTID_RX_THRES_REACH - indicating that the RX FIFO has reached its programmed Trigger Level
UART_INTID_RX_LINE_STAT_ERROR - indicating the occurence of a receiver Line Status error
UART_INTID_CHAR_TIMEOUT - indicating the occurence of a Receiver Timeout
UART_INTID_XOFF_SPEC_CHAR_DETECT - indicating the detection of XOFF or a Special character
UART_INTID_MODEM_SIG_STATE_CHANGE - indicating that atleast one of the Modem signals among CTSn, RTSn and DSRn have changed states from active(low) to inactive(high)

◆ UARTIntPendingStatusGet()

uint32_t UARTIntPendingStatusGet ( uint32_t baseAddr )

This API determines whether any UART interrupt condition is still alive and is pending to be serviced.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: UART_INT_PENDING - if servicing an interrupt is still pending
UART_N0_INT_PENDING - if there are no interrupts to be serviced

◆ UARTInt2StatusGet()

uint32_t UARTInt2StatusGet ( uint32_t baseAddr )

This API determines the UART Interrupt Status 2.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one or a combination of the following macros:

UART_INT2_RX_EMPTY - to enable receive FIFO empty interrupt
UART_INT2_TX_EMPTY - to enable TX FIFO empty interrupt

◆ UARTFIFOEnableStatusGet()

uint32_t UARTFIFOEnableStatusGet ( uint32_t baseAddr )

This API determines whether FIFO mode of operation is enabled for the UART instance or not.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: TRUE - if FIFO mode of operation is enabled
FALSE - if FIFO mode of operation is disabled

◆ UARTAutoRTSAutoCTSControl()

void UARTAutoRTSAutoCTSControl	(	uint32_t	baseAddr,
		uint32_t	autoCtsControl,
		uint32_t	autoRtsControl
	)

This API controls the use of Auto-RTS and Auto-CTS features which are used in Hardware Flow Control Mode of operation. The Auto-RTS and Auto-CTS functions can be individually enabled or disabled.

Parameters

baseAddr	Memory address of the UART instance being used.
autoCtsControl	This specifies whether to enable or disable Auto-CTS functionality
autoRtsControl	This specifies whether to enable or disable Auto-RTS functionality

'autoCtsControl' can take one of the following values:

UART_AUTO_CTS_DISABLE - to disable Auto-CTS functionality
UART_AUTO_CTS_ENABLE - to enable Auto-CTS functionality
'autoRtsControl' can take either of the following values:
UART_AUTO_RTS_DISABLE - to disable Auto-RTS functionality
UART_AUTO_RTS_ENABLE - to enable Auto-RTS functionality

Returns
None.

Note
This API switches UART to Configuration Mode B, programs AUTOCTSEN and AUTORTSEN bits in EFR and reverts the UART back to the original mode of operation.

◆ UARTSpecialCharDetectControl()

void UARTSpecialCharDetectControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API controls the feature of detecting a Special Character arriving in the receiver.

Parameters

baseAddr	Memory address of the UART instance being used.
controlFlag	This specifies whether to enable or disable detection of Special Character.

'controlFlag' can take either of the following two values:

UART_SPECIAL_CHAR_DETECT_DISABLE - to disable detection of Special Character
UART_SPECIAL_CHAR_DETECT_ENABLE - to enable detection of Special Character

Returns
None.

Note
This API switches the UART to Configuration Mode B, programs SPECIALCHARDETECT field in EFR and reverts the UART back to the original mode of operation.

◆ UARTSoftwareFlowCtrlOptSet()

void UARTSoftwareFlowCtrlOptSet	(	uint32_t	baseAddr,
		uint32_t	swFlowCtrl
	)

This API configures the options for Software Flow Control.

Parameters

baseAddr	Memory address of the UART instance being used.
swFlowCtrl	This specifies one of the options available for software flow control.

'swFlowCtrl' can take one of the following values:

UART_NO_SOFTWARE_FLOW_CONTROL - To disable Software Flow control
UART_TX_RX_XON1_XOFF1 - Transmitter transmits XON1, XOFF1; Receiver expects XON1, XOFF1
UART_TX_RX_XON2_XOFF2 - Transmitter transmits XON2, XOFF2; Receiver expects XON2, XOFF2
UART_TX_RX_XON1_XOFF1_XON2_XOFF2 - Transmitter transmits XON1,XON2, XOFF1 and XOFF2; Receiver expects XON1,XON2, XOFF1, XOFF2

Returns
None.

Note
This API switches the UART to Configuration Mode B, programs SWFLOWCONTROL field in EFR and reverts the UART back to the original mode of operation.

◆ UARTHardwareFlowCtrlOptSet()

void UARTHardwareFlowCtrlOptSet	(	uint32_t	baseAddr,
		uint32_t	hwFlowCtrl
	)

This API configures the options for hardware Flow Control.

Parameters

baseAddr	Memory address of the UART instance being used.
hwFlowCtrl	This specifies one of the options available for Hardware flow control.

'hwFlowCtrl' can take one of the following values:

UART_EFR_HW_NO_FLOW_CONTROL_VALUE - To disable Hardware Flow control
UART_EFR_HW_ENABLE_RTS_FLOW_CONTROL_VALUE - Enable only RTS
UART_EFR_HW_ENALE_CTS_FLOW_CONTROL_VALUE - Enable only CTS
UART_EFR_HW_ENABLE_RTS_CTS_FLOW_CONTROL_VALUE - Enable both RTS and CTS

Returns: None.

Note: This API switches the UART to Configuration Mode B, programs HWFLOWCONTROL field in EFR and reverts the UART back to the original mode of operation.

◆ UARTPulseShapingControl()

void UARTPulseShapingControl	(	uint32_t	baseAddr,
		uint32_t	shapeControl
	)

Used only in UART mode, this API is used to control the pulse shaping feature. Pulse shaping feature could either be enabled or disabled in UART mode.

Parameters

baseAddr	Memory address of the UART instance being used.
shapeControl	This specifies whether to enable or disable Pulse shaping feature in UART mode

'shapeControl' can take either of the two following values:

UART_PULSE_NORMAL - to disable Pulse Shaping feature which is the Normal and default configuration
UART_PULSE_SHAPING - to enable Pulse Shaping feature

Returns
None

◆ UARTModuleReset()

void UARTModuleReset ( uint32_t baseAddr )

This API performs a module reset of the UART instance. It also waits until the reset process is complete.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: None.

Note: This API accesses the System Configuration Register(SYSC) and System Status Register(SYSS) to perform module reset and to wait until the same is complete.

◆ UARTIdleModeConfigure()

void UARTIdleModeConfigure	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API can be used to control the Power Management request/acknowledgement process.

Parameters

baseAddr	Memory address of the UART instance being used.
modeFlag	This specifies the Power Management request/acknowledgement process to be followed

'modeFlag' can take one of the following values:

UART_IDLEMODE_FORCE_IDLE - to enable Force Idle mode
UART_IDLEMODE_NO_IDLE - to enable No-Idle mode
UART_IDLEMODE_SMART_IDLE - to enable Smart Idle mode
UART_IDLEMODE_SMART_IDLE_WAKEUP - to enable Smart Idle Wakeup mode

Returns
None

◆ UARTWakeUpControl()

void UARTWakeUpControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API is used to control(enable/disable) the Wake-Up feature of the UART.

Parameters

baseAddr	Memory address of the UART instance being used.
controlFlag	This specifies whether the Wake Up feature should be enabled or disabled for the UART instance

'controlFlag' can take one of the following two values:

UART_WAKEUP_ENABLE - to enable Wake-Up feature
UART_WAKEUP_DISABLE - to disable Wake-Up feature

Returns
None

◆ UARTAutoIdleModeControl()

void UARTAutoIdleModeControl	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API is used to control(enable/disable) the Auto-Idle mode of operation of the UART.

Parameters

baseAddr	Memory address of the UART instance being used.
modeFlag	This specifies whether to enable or disable the Auto-Idle mode of the UART

'modeFlag' can take one of the following two values:

UART_AUTO_IDLE_MODE_DISABLE - to disable Auto-Idle mode
UART_AUTO_IDLE_MODE_ENABLE - to enable Auto-Idle mode

Returns
None

◆ UARTFlowCtrlTrigLvlConfig()

void UARTFlowCtrlTrigLvlConfig	(	uint32_t	baseAddr,
		uint32_t	rtsHaltFlag,
		uint32_t	rtsStartFlag
	)

This API configures the Receiver FIFO threshold level to start/stop transmission during Hardware Flow Control.

Parameters

baseAddr	Memory address of the UART instance being used.
rtsHaltFlag	The receiver FIFO threshold level on attaining which the RTS line is deasserted signalling the transmitter of its counterpart to stop trasmitting.
rtsStartFlag	The receiver FIFO threshold level on attaining which the RTS line is asserted signalling the transmitter of its counterpart to start transmitting.

'rtsHaltFlag' can take one among the following values:

m, where (0 <= m <= 15).
The HALT trigger level would then be (m * 4).
'rtsStartFlag' can take one among the following values:
n, where (0 <= n <= 15).
The RESTORE trigger level would then be (n * 4).
For Example: If m = 8 and n = 5, then the receiver trigger levels would be:
HALT = (8 * 4) = 32, RESTORE = (5 * 4) = 20.

Returns
None.

Note
Here two things should be taken care of:
1> RX FIFO Threshold Level to Halt Transmission should be greater than the Threshold level to Start transmission i.e. TCR[3:0] > TCR[7:4].
2> In FIFO Interrupt mode with Flow Control, the RX FIFO threshold level to Halt Transmission (TCR[3:0]) should be greater than or equal to the Receiver FIFO trigger level(TLR[7:4] or FCR[7:6]).

◆ UARTXON1XOFF1ValProgram()

void UARTXON1XOFF1ValProgram	(	uint32_t	baseAddr,
		uint8_t	xon1Value,
		uint8_t	xoff1Value
	)

This API programs the XON1/ADDR1 and XOFF1 registers.

Parameters

baseAddr	Memory address of the UART instance being used.
xon1Value	The XON1 character.
xoff1Value	The XOFF1 character.

Returns: None.

Note: In UART mode, the character in XON1/ADDR1 register is the XON1 character. In IrDA mode, this is the address ADDR1.

◆ UARTXON2XOFF2ValProgram()

void UARTXON2XOFF2ValProgram	(	uint32_t	baseAddr,
		uint8_t	xon2Value,
		uint8_t	xoff2Value
	)

This API programs the XON2/ADDR2 and XOFF2 registers.

Parameters

baseAddr	Memory address of the UART instance being used.
xon2Value	The XON2 character.
xoff2Value	The XOFF2 character.

Returns: None.

Note: In UART mode, the character in XON2/ADDR2 register is the XON2 character. In IrDA mode, this is the address ADDR2.

◆ UARTXONAnyFeatureControl()

void UARTXONAnyFeatureControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API controls(enables/disables) the XON-any feature in Modem Control Register(MCR).

Parameters

baseAddr	Memory address of the UART instance being used.
controlFlag	This specifies whether to enable or disable XON any feature 'xonAnyControl' can take one of the following values: UART_XON_ANY_ENABLE - to enable XON any functionality UART_XON_ANY_DISABLE - to disable XON any functionality

Returns: None.

Note: When XON-any feature is enabled, the transmission will resume after receiving any character after recognizing the XOFF character. The XON-any character is written into the RX FIFO even if it is a software flow character.

◆ UARTLoopbackModeControl()

void UARTLoopbackModeControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API controls(enables/disables) the Loopback mode of operation for the UART instance.

Parameters

baseAddr	Memory address of the UART instance being used
controlFlag	This specifies whether to enable or disable Loopback mode of operation 'controlFlag' can take one of the following values: UART_LOOPBACK_MODE_ENABLE - to enable Loopback mode of operation UART_LOOPBACK_MODE_DISABLE - to disable Loopback mode and thus resulting in switching to Normal operating mode

Returns: None

◆ UARTModemControlSet()

void UARTModemControlSet	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API switches the specified Modem Control Signals to active state. The Modem Control signals in context are DCD, RI, RTS and DTR.

Parameters

baseAddr	Memory address of the UART instance being used.
modeFlag	This specifies the signals that are required to be switched to active state. Bits MCR[3:0] hold control for switching Modem Control Signals to active/inactive state.

'modeFlag' can take one or a combination of the following values:

UART_DCD_CONTROL - specifying to force DCDn input to active state(low)
UART_RI_CONTROL - specifying to force RIn input to active state(low)
UART_RTS_CONTROL - specifying to force RTSn output to active state (low)
UART_DTR_CONTROL - specifying to force DTRn output to active state (low)

Returns
None.

◆ UARTModemControlClear()

void UARTModemControlClear	(	uint32_t	baseAddr,
		uint32_t	modeFlag
	)

This API switches the specified Modem Control signals to inactive state. The Modem Control signals in context are DCD, RI, RTS and DTR.

Parameters

baseAddr Memory address of the UART instance being used.

modeFlag

This specifies the signals that are required to be switched to inactive state. Bits MCR[3:0] hold control for switching Modem Control Signals to active/inactive state. 'modeFlag' can take one or a combination of the following values:

UART_DCD_CONTROL - specifying to force DCDn input to inactive state(high)
UART_RI_CONTROL - specifying to force RIn input to inactive state (high)
UART_RTS_CONTROL - specifying to force RTSn output to inactive state(high)
UART_DTR_CONTROL - specifying to force DTRn output to inactive state(high)

Returns: None

◆ UARTModemStatusGet()

uint32_t UARTModemStatusGet ( uint32_t baseAddr )

This API reads the values on Modem Signal Lines. The Modem Signals in context are: 1> Data Carrier Detect(DCD)
2> Ring Indicator(RI)
3> Data Set Ready(DSR)
4> Clear To Send(CTS)
.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

The value returned could be one of the following macros, a combination or all of it.

UART_DCD_VALUE - indicating DCDn line is active(low)
UART_RI_VALUE - indicating RIn line is active(low)
UART_DSR_VALUE - indicating DSRn line is active(low)
UART_CTS_VALUE - indicating CTSn line is active(low)

◆ UARTModemStatusChangeCheck()

uint32_t UARTModemStatusChangeCheck ( uint32_t baseAddr )

This API determines if the values on Modem Signal Lines have changed since the last read of Modem Status Register(MSR). The Modem Signals in context are DCD, RI, DSR, CTS.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

The value returned could be one of the following macros, a combination or all of it.

UART_DCD_STS_CHANGED - indicating that DCDn input changed state since the last read of MSR
UART_RI_STS_CHANGED - indicating that RIn input changed state since the last read of MSR
UART_DSR_STS_CHANGED - indicating that DSRn input changed state since the last read of MSR
UART_CTS_STS_CHANGED - indicating that CTSn input changed state since the last read of MSR

◆ UARTResumeOperation()

void UARTResumeOperation ( uint32_t baseAddr )

This API reads the RESUME register which clears the internal flags.

Parameters

baseAddr Memory address of the UART instance being used

Returns: None

Note: UART_RESUME is read only register that always reads 0x0. When conditions like TX Underrun/RX Overrun errors occur, the transmission/reception gets halted and some internal flags are set. Clearing these flags would resume the halted operation. Dummy operations are carried out in this API to remove compiler warnings.

◆ UARTWakeUpEventsEnable()

void UARTWakeUpEventsEnable	(	uint32_t	baseAddr,
		uint32_t	wakeUpFlag
	)

This API enables the Wake-Up capability for the specified events. On enabling Wake-Up capability for them, the occurence of the corresponding event shall wake up the system.

Parameters

baseAddr	Memory address of the UART instance being used.
wakeUpFlag	This specifies the event(s) for which Wake-Up capability needs to be enabled.

'wakeUpFlag' can take one or a combination of the following values:

UART_WAKEUP_TX_INTERRUPT - enabling THR, TXDMA and TXSTATUS interrupts to wake up the system
UART_WAKEUP_RLS_INTERRUPT - enabling the Receiver Line Status interrupt to wake up the system
UART_WAKEUP_RHR_INTERRUPT - enabling the RHR interrupt(RX FIFO threshold level reached) to wake up the system
UART_WAKEUP_RX_ACTIVITY - enabling any activity on the Receiver line (RX) to wake up the system
UART_WAKEUP_DCD_ACTIVITY - enabling any activity on DCD line to wake up the system
UART_WAKEUP_RI_ACTIVITY - enabling any activity on RI line to wake up the system
UART_WAKEUP_DSR_ACTIVITY - enabling any acivity on DSR line to wake up the system
UART_WAKEUP_CTS_ACTIVITY - enabling any activity on CTS line to wake up the system

Returns
None

◆ UARTWakeUpEventsDisable()

void UARTWakeUpEventsDisable	(	uint32_t	baseAddr,
		uint32_t	wakeUpFlag
	)

This API disables the Wake-Up capability for the specified events. On disabling Wake-Up capability for them, the occurence of the corresponding event shall not wake up the system.

Parameters

baseAddr	Memory address of the UART instance being used.
wakeUpFlag	This specifies the event(s) for which Wake-Up capability needs to be disabled.

'wakeUpFlag' can take one or a combination of the following values:

UART_WAKEUP_TX_INTERRUPT - disabling THR, TXDMA and TXSTATUS interrupts to wake up the system
UART_WAKEUP_RLS_INTERRUPT - disabling the Receiver Line Status interrupt to wake up the system
UART_WAKEUP_RHR_INTERRUPT - disabling the RHR interrupt(RX FIFO threshold level reached) to wake up the system
UART_WAKEUP_RX_ACTIVITY - disabling any activity on the Receiver line (RX) to wake up the system
UART_WAKEUP_DCD_ACTIVITY - disabling any activity on DCD line to wake up the system
UART_WAKEUP_RI_ACTIVITY - disabling any activity on RI line to wake up the system
UART_WAKEUP_DSR_ACTIVITY - disabling any acivity on DSR line to wake up the system
UART_WAKEUP_CTS_ACTIVITY - disabling any activity on CTS line to wake up the system

Returns
None

◆ UARTFIFOTrigLvlGranControl()

void UARTFIFOTrigLvlGranControl	(	uint32_t	baseAddr,
		uint32_t	rxFIFOGranCtrl,
		uint32_t	txFIFOGranCtrl
	)

This API controls the feature of setting the Trigger Level granularity as 1 for Transmitter and Receiver FIFOs.

Parameters

baseAddr	Memory address of the UART instance being used.
rxFIFOGranCtrl	This specifies whether the trigger level granularity for the RX FIFO is to be 1 or not
txFIFOGranCtrl	This specifies whether the trigger level granularity for the TX FIFO is to be 1 or not

'rxFIFOGranCtrl' can take either of the following values:

UART_RX_TRIG_LVL_GRAN_1_DISABLE - to disable usage of a granularity of 1 for RX FIFO Trigger level
UART_RX_TRIG_LVL_GRAN_1_ENABLE - to set a granularity of 1 for RX FIFO Trigger level
'txFIFOGranCtrl' can take either of the following values:
UART_TX_TRIG_LVL_GRAN_1_DISABLE - to disable usage of a granularity of 1 for TX FIFO Trigger level
UART_TX_FIFO_LVL_GRAN_1_ENABLE - to set a granularity of 1 for TX FIFO Trigger level

Returns
None

◆ UARTDSRInterruptControl()

void UARTDSRInterruptControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API controls the interrupt enable and disable feature for Data Set Ready(DSRn) interrupt.

Parameters

baseAddr	Memory address of the UART instance being used
controlFlag	This specifies whether to enable or disable DSRn interrupt

'controlFlag' can take one of the following values:

UART_DSRn_INT_DISABLE - to disable DSRn interrupt
UART_DSRn_INT_ENABLE - to enable DSRn interrupt

Returns
None

◆ UARTTxEmptyIntControl()

void UARTTxEmptyIntControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API is used to choose a condition under which a Transmit Holding Register(THR) Interrupt should occur. A THR interrupt can be configured to occur either when:
1> TX FIFO becoming empty OR
2> TX FIFO and TX Shift register becoming empty.

Parameters

baseAddr	Memory address of the UART instance being used
controlFlag	This specifies the condition under which a Transmitter Holding Register Interrupt should occur.

'controlFlag' can take either of the following two values:

UART_THR_INT_NORMAL - for THR Interrupt to be raised under normal conditions(guided by the TX FIFO Threshold value)
UART_THR_INT_FIFO_TSR_EMPTY - for THR Interrupt to be raised when both Transmitter FIFO and Transmitter Shift Register are empty

Returns
None

◆ UARTRXCTSDSRWakeUpConfigure()

void UARTRXCTSDSRWakeUpConfigure	(	uint32_t	baseAddr,
		uint32_t	wakeUpFlag
	)

This API controls (enables/disables) a feature where a falling edge on the RX, CTSn or DSRs could send a wake-up interrupt to the CPU.

Parameters

baseAddr	Memory address of the UART instance being used.
wakeUpFlag	This specifies whether or not a wake-up interrupt should be sent to the CPU when a falling edge occurs on RX, CTSn or DSRn lines.

'wakeUpFlag' can take one of the following values:

UART_RX_CTS_DSR_WAKEUP_DISABLE - to disable generation of a Wake-Up interrupt due to occurence of a falling edge on RX, CTSn or DSRn lines.
UART_RX_CTS_DSR_WAKEUP_ENABLE - to enable generation of a Wake-Up interrupt due to occurence of a falling edge on RX, CTSn, DSRn lines.

Returns: None

◆ UARTRXCTSDSRTransitionStatusGet()

uint32_t UARTRXCTSDSRTransitionStatusGet ( uint32_t baseAddr )

This API determines whether a falling edge occured on RX, CTSn or DSRn lines.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one of the following values:

UART_RX_CTS_DSR_NO_FALL_EDGE - indicating that no falling edge occured on RX, CTSn and DSRn lines
UART_RX_CTS_DSR_FALL_EDGE - indicating that a falling edge occured on RX, CTSn and DSRn lines

◆ UARTDMACounterResetControl()

void UARTDMACounterResetControl	(	uint32_t	baseAddr,
		uint32_t	controlFlag
	)

This API controls the DMA Counter Reset options.

Parameters

baseAddr	Memory address of the UART instance being used
controlFlag	This specifies the DMA Counter Reset options

'controlFlag' can take either of the following values:

UART_DMA_CNTR_NO_RESET_FIFO_RESET - indicating that the DMA counter shall not be reset if the corresponding FIFO is reset
UART_DMA_CNTR_RESET_FIFO_RESET - indicating that the DMA counter shall be reset if the corresponding FIFO is reset

Returns
None

◆ UARTTxFIFOFullStatusGet()

uint32_t UARTTxFIFOFullStatusGet ( uint32_t baseAddr )

This API determines whether the Transmitter FIFO is full or not.

Parameters

baseAddr Memory address of the UART instance being used

Returns

This returns either of the following values:

UART_TX_FIFO_NOT_FULL - indicating that the TX FIFO is not full
UART_TX_FIFO_FULL - indicating that the TX FIFO is full

◆ UARTTxFIFOLevelGet()

uint32_t UARTTxFIFOLevelGet ( uint32_t baseAddr )

This API determines the current level of the Transmitter FIFO.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The current level of the Transmitter FIFO.

◆ UARTRxFIFOLevelGet()

uint32_t UARTRxFIFOLevelGet ( uint32_t baseAddr )

This API determines the current level of the Receiver FIFO.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The current level of the Receiver FIFO.

◆ UARTAutobaudParityGet()

uint32_t UARTAutobaudParityGet ( uint32_t baseAddr )

This API determines the Parity mode being configured by the system in the UART Autobauding mode.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one of the following values:

UART_AUTOBAUD_NO_PARITY - indicating that no parity was identified
UART_AUTOBAUD_PARITY_SPACE - indicating that space parity has been configured
UART_AUTOBAUD_EVEN_PARITY - indicating that even parity has been configured
UART_AUTOBAUD_ODD_PARITY - indicating that odd parity has been configured

Note: UASR register used in this API can be accessed only when the UART is in Configuration Mode A or Configuration Mode B of operation.

◆ UARTAutobaudWordLenGet()

uint32_t UARTAutobaudWordLenGet ( uint32_t baseAddr )

This API determines the word length per frame(character length) being configured by the system in UART Autobauding mode.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one of the following two values:

UART_AUTOBAUD_CHAR_LENGTH_7 - indicating word length of 7 bits
UART_AUTOBAUD_CHAR_LENGTH_8 - indicating word length of 8 bits

Note: UASR register used in this API can be accessed only when the UART is in Configuration Mode A or Configuration Mode B of operation.

◆ UARTAutobaudSpeedGet()

uint32_t UARTAutobaudSpeedGet ( uint32_t baseAddr )

This API determines the baud rate being configured by the system in UART Autobauding mode.

Parameters

baseAddr Memory address of the UART instance being used.

Returns

This returns one of the following values:

UART_AUTOBAUD_SPEED_115200 - for baud rate of 115200 bps
UART_AUTOBAUD_SPEED_57600 - for baud rate of 57600 bps
UART_AUTOBAUD_SPEED_38400 - for baud rate of 38400 bps
UART_AUTOBAUD_SPEED_28800 - for baud rate of 28800 bps
UART_AUTOBAUD_SPEED_19200 - for baud rate of 19200 bps
UART_AUTOBAUD_SPEED_14400 - for baud rate of 14400 bps
UART_AUTOBAUD_SPEED_9600 - for baud rate of 9600 bps
UART_AUTOBAUD_SPEED_4800 - for baud rate of 4800 bps
UART_AUTOBAUD_SPEED_2400 - for baud rate of 2400 bps
UART_AUTOBAUD_SPEED_1200 - for baud ratebaud rate of 1200 bps
UART_AUTOBAUD_NO_SPEED_IDEN - for no speed identified

Note: UASR register used in this API can be accessed only when the UART is in Configuration Mode A or Configuration Mode B of operation.

◆ UARTScratchPadRegWrite()

void UARTScratchPadRegWrite	(	uint32_t	baseAddr,
		uint32_t	scratchValue
	)

This API programs the Scratchpad Register with the specified value.

Parameters

baseAddr	Memory address of the UART instance being used
scratchValue	This is the scratch value(temporary data) to be loaded to the Scratchpad Register

Returns: None

◆ UARTScratchPadRegRead()

uint32_t UARTScratchPadRegRead ( uint32_t baseAddr )

This API reads the value in Scratchpad Register.

Parameters

baseAddr Memory address of the UART instance being used

Returns: The value in Scratchpad Register

◆ UARTModuleVersionNumberGet()

uint32_t UARTModuleVersionNumberGet ( uint32_t baseAddr )

This API reads the Revision Number of the module from the Module Version Register(MVR).

Parameters

baseAddr Memory address of the UART instance being used

Returns: This returns the Major Revision Number(MVR[7:4] and Minor Revision Number(MVR[3:0])) of the module.

◆ UARTFIFORegisterWrite()

void UARTFIFORegisterWrite	(	uint32_t	baseAddr,
		uint32_t	fcrValue
	)

This API is used to write a specified value to the FIFO Control Register(FCR).

Parameters

baseAddr	Memory address of the UART instance being used.
fcrValue	This specifies the value to be written to the FCR.

'fcrValue' can be determined using a parameterized macro named 'UART_FCR_PROGRAM'. The parameters of 'UART_FCR_PROGRAM' are described below:

rxFIFOTrig - specifies the Receiver FIFO Trigger Level
txFIFOTrig - specifies the Transmitter FIFO Trigger Level
dmaMode - specifies the DMA Mode of operation to be selected:
Write 0 - for DMA Mode 0
1 - for DMA Mode 1
txClr - specifies whether or not to clear the Transmitter FIFO and resetting the counter logic to 0.
rxClr - specifies whether or not to clear the Receiver FIFO and resetting the counter logic to 0.
fifoEn - specifies whether to enable the FIFO mode for the UART or not
0 - to enable Non-FIFO mode of operation
1 - to enable FIFO mode of operation

Returns
None

Note
1> The FIFO_EN and DMA_MODE bits of FCR can be written to only when the Baud Clock is not running(DLL and DLH register are cleared to 0). Modifying DLL and DLH registers in turn requires that the UART be operated in Disabled Mode(MDR1[2:0] = 0x7).
2> Writing to 'TX_FIFO_TRIG' field in FCR requires that the ENHANCEDEN bit in EFR(EFR[4]) be set to 1.
Prior to writing to the FCR, this API does the above two operations. It also restores the respective bit values after FCR has been written to.

◆ UARTTxDMAThresholdControl()

void UARTTxDMAThresholdControl	(	uint32_t	baseAddr,
		uint32_t	thrsCtrlFlag
	)

This function controls the method of setting the Transmit DMA Threshold Value. The Transmit DMA Threshold Value can be set to a default value of 64 characters or can take the value in TX_DMA_THRESHOLD register.

Parameters

baseAddr	Memory address of the UART instance being used.
thrsCtrlFlag	A value which signifies the method of setting the Transmit DMA Threshold Value.

'thrsCtrlFlag' can take one of the following values:

UART_TX_DMA_THRESHOLD_64 - for 64 characters TX DMA Threshold value
UART_TX_DMA_THRESHOLD_REG - for Transmit DMA Threshold value to be the value in TX_DMA_THRESHOLD register.

Returns
None

◆ UARTTxDMAThresholdValConfig()

void UARTTxDMAThresholdValConfig	(	uint32_t	baseAddr,
		uint32_t	thrsValue
	)

This function programs the TX_DMA_THRESHOLD register which holds Transmit DMA Threshold value to be used. When a TX DMA Threshold value other than 64 characters is required, this function can be used to program the same.

Parameters

baseAddr	Memory address of the UART instance being used.
thrsValue	The Transmit DMA Threshold Value.

'thrsValue' can take one of the following value - (0 <= thrsValue <= 63).

Returns: None

◆ UARTFIFOLevelSet()

void UARTFIFOLevelSet	(	uint32_t	baseAddr,
		uint32_t	rxLevel
	)

This function sets the receiver FIFO trigger level.
.

Parameters

baseAddr	Memory address of the UART instance used.
rxLevel	This contains the settings for the FIFO threshold level. While setting the FIFO threshold, it shall be assumed that the FIFO is being enabled.This can take one of the four following values: 1> UART_RX_TRIG_LEVEL_1 2> UART_RX_TRIG_LEVEL_4 3> UART_RX_TRIG_LEVEL_8 4> UART_RX_TRIG_LEVEL_14

Returns: None.

Note: This API needs needs to be called to configure the FIFO without enabling the DMA mode. If DMA mode is being used, the UARTDMAEnable() should be used to configure the FIFO.; FIFO Control Register(FCR) and the Interrupt Identification Register (IIR) share a common offset address. FCR register has write-only
permissions and IIR register has read-only permissions. Therefore, reading from this address will read the value in IIR register and
writing to this address will write the value into the FCR register. Since these share the same address, the integrity of bits in FCR
register are at risk if we read from IIR register, modify this value and write the new value into the FCR register. Thus, we retain the status of the FIFOEN bit and the RXFIFTL bit in the FCR register by reinstating them to their previous values.

◆ UARTModemControlGet()

uint32_t UARTModemControlGet ( uint32_t baseAddr )

This function gets the status of the RTS and AFE bits in the MCR register.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: The status of RTS and AFE bits if MCR

◆ UARTFIFOCtrlRegWrite()

void UARTFIFOCtrlRegWrite	(	uint32_t	baseAddr,
		uint32_t	fcrValue
	)

This API is used to write a specified value to the FIFO Control Register(FCR) without disabling the divisor values. Preferable setting FCR during runtime.

Parameters

baseAddr	Memory address of the UART instance being used.
fcrValue	This specifies the value to be written to the FCR.

◆ UARTModemControlReset()

void UARTModemControlReset ( uint32_t baseAddr )

This API resets the Modem control register.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: None.

◆ UARTReadStatus()

uint32_t UARTReadStatus ( uint32_t baseAddr )

This API reads the line status register value.

Parameters

baseAddr Memory address of the UART instance being used.

Returns: This returns the line status register value.

◆ UARTIsTransmitterEmpty()

uint32_t UARTIsTransmitterEmpty ( uint32_t baseAddr )

This API returns the transmitter empty status i.e. if Transmitter FIFO (THR register in non-FIFO mode) and Transmitter Shift Register are empty.

Parameters

baseAddr Memory address of the UART instance being used

Returns: Transmitter empty status TRUE: Transmitter is empty FALSE: Transmitter is not empty

◆ UARTCharGetNonBlocking2()

uint32_t UARTCharGetNonBlocking2	(	uint32_t	baseAddr,
		uint8_t *	pChar
	)

This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is ready to be read.

Parameters

baseAddr	Memory address of the UART instance being used.
pChar	Pointer to the byte variable which saves the byte read from RBR if there is any char ready to be read

Returns: If the RX FIFO(or RHR) was found to have atleast one byte of data, then this API returns TRUE. Else it returns FALSE.

◆ UARTCharGetTimeout2()

uint32_t UARTCharGetTimeout2	(	uint32_t	baseAddr,
		uint32_t	timeOutVal,
		uint8_t *	pChar
	)

This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeout value gets decremented to zero, whichever happens first.This is a replacement for the UARTCharGetTimeout which will incorrectly return timeout if the UART receives 0xFF as data.

Parameters

baseAddr	Memory address of the UART instance being used.
timeOutVal	The timeout value that is to be used. This timeout value gets decremented once per iteration of the wait loop. wait loop.
pChar	Pointer to the byte variable which saves the byte read from RHR if there is any char ready to be read

Returns: This returns either of the below two values:
1) If a character was read in before the timeout value gets decremented to zero, this API returns TRUE.
2) If no character was read within the timeout value getting decremented to zero, this API returns FASLE.

◆ UARTDirPolSet()

void UARTDirPolSet	(	uint32_t	baseAddr,
		uint32_t	dirPol
	)

This API is used to set the RS-485 External Transceiver Direction Polarity.

Parameters

baseAddr	Memory address of the UART instance being used.
dirPol	Direction Polarity value UART_MDR3_DIR_POL_0 ==> TX: RTS=0, RX: RTS=1 UART_MDR3_DIR_POL_1 ==> TX: RTS=1, RX: RTS=0

Returns: None.

◆ UARTDirEnControl()

void UARTDirEnControl	(	uint32_t	baseAddr,
		uint32_t	dirEnFlag
	)

This API is used to control the RS-485 External Transceiver Direction.

Parameters

baseAddr	Memory address of the UART instance being used.
dirEnFlag	TRUE: enable direction, FALSE: disable direction.

Returns: None.

◆ UARTSetTimeOutValue()

void UARTSetTimeOutValue	(	uint32_t	baseAddr,
		uint16_t	timeoutIntrVal,
		uint32_t	timeoutBehavior
	)

This API is used to set the timeout value and the TIMEOUT_BEHAVE.

Parameters

baseAddr	Memory address of the UART instance being used.
timeoutIntrVal	16bit value of the timeout.
timeoutBehavior	TIMEOUT_BEHAVE to be set. timeoutBehavior can take the following values: UART_TIMEOUT_COUNTER_RESET: Reset counter on any activity on RX lines. UART_TIMEOUT_COUNTER_NO_CHANGE: Do not reset counter on any activity on RX lines.

Returns: None.

Introduction

Files

Functions

The size of the Transmitter FIFO.

The size of the Receiver FIFO.

Values to configure the Operating modes of UART.

Values to configure Timeout Behaviour for UART.

Values to control the Line characteristics.

Values to control parity feature.

Values associated with setting the Trigger Levels and DMA mode

Values related to enabling/disabling of Interrupts.

Values related to Line Status information.

Values related to status of Interrupt souces.

Values pertaining to control of Enhanced Features.

Values corresponding to Mode Definition Register 2(MDR2).

Values corresponding to Mode Definition Register 3(MDR3).

Macros related to control and status of Modem Signals.

Values related to the control and status of Supplementary registers.

Values related to Auxilliary Control Register(ACREG).

Values controlling System Configuration functions.

Values configuring Wake-up modes for the UART in Wake-Up Enable

Values indicating the line characteristics of UART Autobauding mode

Miscellaneous macros.

Macro Definition Documentation

◆ TX_FIFO_SIZE

◆ RX_FIFO_SIZE

◆ UART16x_OPER_MODE

◆ UART_SIR_OPER_MODE

◆ UART16x_AUTO_BAUD_OPER_MODE

◆ UART13x_OPER_MODE

◆ UART_MIR_OPER_MODE

◆ UART_FIR_OPER_MODE

◆ UART_CIR_OPER_MODE

◆ UART_DISABLED_MODE

◆ UART_TIMEOUT_COUNTER_RESET

◆ UART_TIMEOUT_COUNTER_NO_CHANGE

◆ UART_BREAK_COND_DISABLE

◆ UART_BREAK_COND_ENABLE

◆ UART_PARITY_REPR_1

◆ UART_PARITY_REPR_0

◆ UART_ODD_PARITY

◆ UART_EVEN_PARITY

◆ UART_PARITY_NONE

◆ UART_FRAME_NUM_STB_1

◆ UART_FRAME_NUM_STB_1_5_2

◆ UART_FRAME_WORD_LENGTH_5

◆ UART_FRAME_WORD_LENGTH_6

◆ UART_FRAME_WORD_LENGTH_7

◆ UART_FRAME_WORD_LENGTH_8

◆ UART_FCR_RX_TRIG_LVL_8

◆ UART_FCR_RX_TRIG_LVL_16

◆ UART_FCR_RX_TRIG_LVL_56

◆ UART_FCR_RX_TRIG_LVL_60

◆ UART_FCR_TX_TRIG_LVL_8

◆ UART_FCR_TX_TRIG_LVL_16

◆ UART_FCR_TX_TRIG_LVL_32

◆ UART_FCR_TX_TRIG_LVL_56

◆ UART_DMA_MODE_0_ENABLE

◆ UART_DMA_MODE_1_ENABLE

◆ UART_DMA_MODE_2_ENABLE

◆ UART_DMA_MODE_3_ENABLE

◆ UART_DMA_EN_PATH_FCR

◆ UART_DMA_EN_PATH_SCR

◆ UART_INT_CTS

◆ UART_INT_RTS

◆ UART_INT_XOFF

◆ UART_INT_SLEEPMODE

◆ UART_INT_MODEM_STAT

◆ UART_INT_LINE_STAT

◆ UART_INT_THR

◆ UART_INT_RHR_CTI

◆ UART_INT2_RX_EMPTY

◆ UART_INT2_TX_EMPTY

◆ UART_FIFO_PE_FE_BI_DETECTED

◆ UART_BREAK_DETECTED_ERROR

◆ UART_FRAMING_ERROR

◆ UART_PARITY_ERROR

◆ UART_OVERRUN_ERROR

◆ UART_INTID_MODEM_STAT

◆ UART_INTID_TX_THRES_REACH