Introduction

Files
file	csl_vtm_pvt_sensor.h
	Header file containing various enumerations, structure definitions and function declarations for the Voltage and Thermal Monitor (VTM) PVT Sensor Workaround.

Typedefs
typedef int8_t	CSL_vtm_err_id

Macros
#define	CSL_VTM_NUM_OF_SENSOR_WA_COMP (1)

#define	CSL_VTM_NUM_OF_ADC_CODES (1024)

#define	CSL_VTM_VALUES_ARE_UNINITIALIZED (-1)

#define	CSL_VTM_ERR_ID_N40 (0)

#define	CSL_VTM_ERR_ID_P30 (1)

#define	CSL_VTM_ERR_ID_P125 (2)

#define	CSL_VTM_ERR_ID_P150 (3)

#define	CSL_VTM_REG_READ_DELAY (5000)

#define	CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MIN (-42000)

#define	CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MAX (158000)

#define	CSL_VTM_NUM_EFUSE_REGS (4u)

#define	CSL_VTM_EFUSE0_S0_N40_MASK (0x0000003FU)

#define	CSL_VTM_EFUSE0_S0_N40_SHIFT (0x00000000U)

#define	CSL_VTM_EFUSE0_S0_N40_SIGN_BIT_MASK (0x00000020U)

#define	CSL_VTM_EFUSE2_S0_P30_MASK (0x001FE000U)

#define	CSL_VTM_EFUSE2_S0_P30_SHIFT (0x0000000DU)

#define	CSL_VTM_EFUSE2_S0_P30_SIGN_BIT_MASK (0x00000080U)

#define	CSL_VTM_EFUSE1_S0_P125_MASK (0x000001FFU)

#define	CSL_VTM_EFUSE1_S0_P125_SHIFT (0x00000000U)

#define	CSL_VTM_EFUSE1_S0_P125_SIGN_BIT_MASK (0x00000100U)

#define	CSL_VTM_EFUSE0_S1_N40_MASK (0x00000FC0U)

#define	CSL_VTM_EFUSE0_S1_N40_SHIFT (0x000000006U)

#define	CSL_VTM_EFUSE0_S2_N40_MASK (0x0003F000U)

#define	CSL_VTM_EFUSE0_S2_N40_SHIFT (0x0000000CU)

#define	CSL_VTM_EFUSE0_S3_N40_MASK (0x00FC0000U)

#define	CSL_VTM_EFUSE0_S3_N40_SHIFT (0x00000012U)

#define	CSL_VTM_EFUSE0_S4_N40_MASK (0x3F000000U)

#define	CSL_VTM_EFUSE0_S4_N40_SHIFT (0x00000018U)

Macro Definition Documentation

◆ CSL_VTM_NUM_OF_SENSOR_WA_COMP

#define CSL_VTM_NUM_OF_SENSOR_WA_COMP (1)

◆ CSL_VTM_NUM_OF_ADC_CODES

#define CSL_VTM_NUM_OF_ADC_CODES (1024)

◆ CSL_VTM_VALUES_ARE_UNINITIALIZED

#define CSL_VTM_VALUES_ARE_UNINITIALIZED (-1)

◆ CSL_VTM_ERR_ID_N40

#define CSL_VTM_ERR_ID_N40 (0)

◆ CSL_VTM_ERR_ID_P30

#define CSL_VTM_ERR_ID_P30 (1)

◆ CSL_VTM_ERR_ID_P125

#define CSL_VTM_ERR_ID_P125 (2)

◆ CSL_VTM_ERR_ID_P150

#define CSL_VTM_ERR_ID_P150 (3)

◆ CSL_VTM_REG_READ_DELAY

#define CSL_VTM_REG_READ_DELAY (5000)

◆ CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MIN

#define CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MIN (-42000)

◆ CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MAX

#define CSL_VTM_TEMPERATURE_MILLI_DEGREE_C_MAX (158000)

◆ CSL_VTM_NUM_EFUSE_REGS

#define CSL_VTM_NUM_EFUSE_REGS (4u)

◆ CSL_VTM_EFUSE0_S0_N40_MASK

#define CSL_VTM_EFUSE0_S0_N40_MASK (0x0000003FU)

◆ CSL_VTM_EFUSE0_S0_N40_SHIFT

#define CSL_VTM_EFUSE0_S0_N40_SHIFT (0x00000000U)

◆ CSL_VTM_EFUSE0_S0_N40_SIGN_BIT_MASK

#define CSL_VTM_EFUSE0_S0_N40_SIGN_BIT_MASK (0x00000020U)

◆ CSL_VTM_EFUSE2_S0_P30_MASK

#define CSL_VTM_EFUSE2_S0_P30_MASK (0x001FE000U)

◆ CSL_VTM_EFUSE2_S0_P30_SHIFT

#define CSL_VTM_EFUSE2_S0_P30_SHIFT (0x0000000DU)

◆ CSL_VTM_EFUSE2_S0_P30_SIGN_BIT_MASK

#define CSL_VTM_EFUSE2_S0_P30_SIGN_BIT_MASK (0x00000080U)

◆ CSL_VTM_EFUSE1_S0_P125_MASK

#define CSL_VTM_EFUSE1_S0_P125_MASK (0x000001FFU)

◆ CSL_VTM_EFUSE1_S0_P125_SHIFT

#define CSL_VTM_EFUSE1_S0_P125_SHIFT (0x00000000U)

◆ CSL_VTM_EFUSE1_S0_P125_SIGN_BIT_MASK

#define CSL_VTM_EFUSE1_S0_P125_SIGN_BIT_MASK (0x00000100U)

◆ CSL_VTM_EFUSE0_S1_N40_MASK

#define CSL_VTM_EFUSE0_S1_N40_MASK (0x00000FC0U)

◆ CSL_VTM_EFUSE0_S1_N40_SHIFT

#define CSL_VTM_EFUSE0_S1_N40_SHIFT (0x000000006U)

◆ CSL_VTM_EFUSE0_S2_N40_MASK

#define CSL_VTM_EFUSE0_S2_N40_MASK (0x0003F000U)

◆ CSL_VTM_EFUSE0_S2_N40_SHIFT

#define CSL_VTM_EFUSE0_S2_N40_SHIFT (0x0000000CU)

◆ CSL_VTM_EFUSE0_S3_N40_MASK

#define CSL_VTM_EFUSE0_S3_N40_MASK (0x00FC0000U)

◆ CSL_VTM_EFUSE0_S3_N40_SHIFT

#define CSL_VTM_EFUSE0_S3_N40_SHIFT (0x00000012U)

◆ CSL_VTM_EFUSE0_S4_N40_MASK

#define CSL_VTM_EFUSE0_S4_N40_MASK (0x3F000000U)

◆ CSL_VTM_EFUSE0_S4_N40_SHIFT

#define CSL_VTM_EFUSE0_S4_N40_SHIFT (0x00000018U)

Typedef Documentation

◆ CSL_vtm_err_id

typedef int8_t CSL_vtm_err_id