PDK API Guide for J721E
Files | Macros
HW ADC
CSL-FL » ADC CSL-FL

Introduction

Files

file  hw_adc.h
 

Macros

#define ADC_REVISION   (0x0U)
 
#define ADC_SYSCONFIG   (0x10U)
 
#define ADC_IRQSTATUS_RAW   (0x24U)
 
#define ADC_IRQSTATUS   (0x28U)
 
#define ADC_IRQENABLE_SET   (0x2cU)
 
#define ADC_IRQENABLE_CLR   (0x30U)
 
#define ADC_IRQWAKEUP   (0x34U)
 
#define ADC_DMAENABLE_SET   (0x38U)
 
#define ADC_DMAENABLE_CLR   (0x3cU)
 
#define ADC_CTRL   (0x40U)
 
#define ADC_ADCSTAT   (0x44U)
 
#define ADC_ADCRANGE   (0x48U)
 
#define ADC_CLKDIV   (0x4cU)
 
#define ADC_MISC   (0x50U)
 
#define ADC_STEPENABLE   (0x54U)
 
#define ADC_IDLECONFIG   (0x58U)
 
#define ADC_TS_CHARGE_STEPCONFIG   (0x5cU)
 
#define ADC_TS_CHARGE_DELAY   (0x60U)
 
#define ADC_IRQ_EOI   (0x20U)
 
#define ADC_STEPCONFIG(m)   ((uint32_t)0x64U + ((m) * 0x8U))
 
#define ADC_STEPCONFIG_NUM_ELEMS   (16U)
 
#define ADC_STEPDELAY(m)   ((uint32_t)0x68U + ((m) * 0x8U))
 
#define ADC_STEPDELAY_NUM_ELEMS   (16U)
 
#define ADC_FIFOCOUNT(m)   ((uint32_t)0xe4U + ((m) * 0xcU))
 
#define ADC_FIFOCOUNT_NUM_ELEMS   (2U)
 
#define ADC_FIFOTHRESHOLD(m)   ((uint32_t)0xe8U + ((m) * 0xcU))
 
#define ADC_FIFOTHRESHOLD_NUM_ELEMS   (2U)
 
#define ADC_DMAREQ(m)   ((uint32_t)0xecU + ((m) * 0xcU))
 
#define ADC_DMAREQ_NUM_ELEMS   (2U)
 
#define ADC_FIFODATA(m)   ((uint32_t)0x100U + ((m) * 0x100U))
 
#define ADC_FIFODATA_NUM_ELEMS   (2U)
 
#define ADC_REVISION_X_MAJOR_SHIFT   (8U)
 
#define ADC_REVISION_X_MAJOR_MASK   (0x00000700U)
 
#define ADC_REVISION_FUNC_SHIFT   (16U)
 
#define ADC_REVISION_FUNC_MASK   (0x0fff0000U)
 
#define ADC_REVISION_R_RTL_SHIFT   (11U)
 
#define ADC_REVISION_R_RTL_MASK   (0x0000f800U)
 
#define ADC_REVISION_RESERVED0_SHIFT   (28U)
 
#define ADC_REVISION_RESERVED0_MASK   (0x30000000U)
 
#define ADC_REVISION_SCHEME_SHIFT   (30U)
 
#define ADC_REVISION_SCHEME_MASK   (0xc0000000U)
 
#define ADC_REVISION_CUSTOM_SHIFT   (6U)
 
#define ADC_REVISION_CUSTOM_MASK   (0x000000c0U)
 
#define ADC_REVISION_Y_MINOR_SHIFT   (0U)
 
#define ADC_REVISION_Y_MINOR_MASK   (0x0000003fU)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_SHIFT   (2U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_MASK   (0x00000004U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_THR_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SHIFT   (7U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_MASK   (0x00000080U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SHIFT   (1U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_MASK   (0x00000002U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SHIFT   (0U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_MASK   (0x00000001U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_RESERVED0_SHIFT   (11U)
 
#define ADC_IRQSTATUS_RAW_RESERVED0_MASK   (0xfffff800U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SET   (1U)
 
#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SHIFT   (6U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_MASK   (0x00000040U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SHIFT   (4U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_MASK   (0x00000010U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SHIFT   (3U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_MASK   (0x00000008U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SHIFT   (8U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_MASK   (0x00000100U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SHIFT   (10U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_MASK   (0x00000400U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_SHIFT   (9U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_MASK   (0x00000200U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_SET   (1U)
 
#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_SHIFT   (5U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_MASK   (0x00000020U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_RAW_FIFO1_THR_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_RESERVED0_SHIFT   (11U)
 
#define ADC_IRQSTATUS_RESERVED0_MASK   (0xfffff800U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_SHIFT   (1U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_MASK   (0x00000002U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_END_OF_SEQUENCE_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_SHIFT   (0U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_MASK   (0x00000001U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_SET_EVT   (1U)
 
#define ADC_IRQSTATUS_AFE_EOC_MISSING_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_SHIFT   (9U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_MASK   (0x00000200U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_NO_PEND   (0U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_CLR   (1U)
 
#define ADC_IRQSTATUS_PEN_UP_EVT_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_SHIFT   (7U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_MASK   (0x00000080U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO1_THR_SHIFT   (5U)
 
#define ADC_IRQSTATUS_FIFO1_THR_MASK   (0x00000020U)
 
#define ADC_IRQSTATUS_FIFO1_THR_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO1_THR_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO1_THR_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO1_THR_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_SHIFT   (6U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_MASK   (0x00000040U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO1_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_SHIFT   (4U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_MASK   (0x00000010U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_PEND   (1U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND   (0U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_CLR   (1U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_PEND   (1U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_PEND   (0U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_CLR   (1U)
 
#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_SHIFT   (3U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_MASK   (0x00000008U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO0_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_SHIFT   (8U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_MASK   (0x00000100U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_OUT_OF_RANGE_NO_ACTION   (0U)
 
#define ADC_IRQSTATUS_FIFO0_THR_SHIFT   (2U)
 
#define ADC_IRQSTATUS_FIFO0_THR_MASK   (0x00000004U)
 
#define ADC_IRQSTATUS_FIFO0_THR_EVT_PEND   (1U)
 
#define ADC_IRQSTATUS_FIFO0_THR_NO_EVT_PEND   (0U)
 
#define ADC_IRQSTATUS_FIFO0_THR_CLR_EVT   (1U)
 
#define ADC_IRQSTATUS_FIFO0_THR_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_SHIFT   (4U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_MASK   (0x00000010U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_SHIFT   (6U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_MASK   (0x00000040U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_SHIFT   (3U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_MASK   (0x00000008U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_SHIFT   (5U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_MASK   (0x00000020U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_THR_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_SHIFT   (7U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_MASK   (0x00000080U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_SHIFT   (2U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_MASK   (0x00000004U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_FIFO0_THR_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_RESERVED0_SHIFT   (11U)
 
#define ADC_IRQENABLE_SET_RESERVED0_MASK   (0xfffff800U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_SHIFT   (9U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_MASK   (0x00000200U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_PEN_UP_EVT_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_SHIFT   (1U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_MASK   (0x00000002U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_SHIFT   (0U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_MASK   (0x00000001U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_EVT_PEND   (1U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_EVT_PEND   (0U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_SET_EVT   (1U)
 
#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_SHIFT   (8U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_MASK   (0x00000100U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_OUT_OF_RANGE_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLED   (1U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_DISABLED   (0U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLE   (1U)
 
#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_SHIFT   (3U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_MASK   (0x00000008U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_SHIFT   (5U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_MASK   (0x00000020U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_THR_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_SHIFT   (4U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_MASK   (0x00000010U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_SHIFT   (9U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_MASK   (0x00000200U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_PEN_UP_EVT_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_SHIFT   (1U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_MASK   (0x00000002U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SHIFT   (0U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_MASK   (0x00000001U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_EVT_PEND   (1U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_EVT_PEND   (0U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SET_EVT   (1U)
 
#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_RESERVED0_SHIFT   (11U)
 
#define ADC_IRQENABLE_CLR_RESERVED0_MASK   (0xfffff800U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_SHIFT   (7U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_MASK   (0x00000080U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_SHIFT   (8U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_MASK   (0x00000100U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_SHIFT   (6U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_MASK   (0x00000040U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_NO_ACTION   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_SHIFT   (2U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_MASK   (0x00000004U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_ENABLED   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_DISABLED   (0U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_DISABLE   (1U)
 
#define ADC_IRQENABLE_CLR_FIFO0_THR_NO_ACTION   (0U)
 
#define ADC_IRQWAKEUP_WAKEEN0_SHIFT   (0U)
 
#define ADC_IRQWAKEUP_WAKEEN0_MASK   (0x00000001U)
 
#define ADC_IRQWAKEUP_WAKEEN0_DISABLED   (0U)
 
#define ADC_IRQWAKEUP_WAKEEN0_ENABLED   (1U)
 
#define ADC_IRQWAKEUP_RESERVED0_SHIFT   (1U)
 
#define ADC_IRQWAKEUP_RESERVED0_MASK   (0xfffffffeU)
 
#define ADC_DMAENABLE_SET_EN_0_SHIFT   (0U)
 
#define ADC_DMAENABLE_SET_EN_0_MASK   (0x00000001U)
 
#define ADC_DMAENABLE_SET_EN_0_ENABLED   (1U)
 
#define ADC_DMAENABLE_SET_EN_0_DISABLED   (0U)
 
#define ADC_DMAENABLE_SET_EN_0_ENABLE   (1U)
 
#define ADC_DMAENABLE_SET_EN_0_NO_ACTION   (0U)
 
#define ADC_DMAENABLE_SET_RESERVED0_SHIFT   (2U)
 
#define ADC_DMAENABLE_SET_RESERVED0_MASK   (0xfffffffcU)
 
#define ADC_DMAENABLE_SET_EN_1_SHIFT   (1U)
 
#define ADC_DMAENABLE_SET_EN_1_MASK   (0x00000002U)
 
#define ADC_DMAENABLE_SET_EN_1_ENABLED   (1U)
 
#define ADC_DMAENABLE_SET_EN_1_DISABLED   (0U)
 
#define ADC_DMAENABLE_SET_EN_1_ENABLE   (1U)
 
#define ADC_DMAENABLE_SET_EN_1_NO_ACTION   (0U)
 
#define ADC_DMAENABLE_CLR_RESERVED0_SHIFT   (2U)
 
#define ADC_DMAENABLE_CLR_RESERVED0_MASK   (0xfffffffcU)
 
#define ADC_DMAENABLE_CLR_EN_1_SHIFT   (1U)
 
#define ADC_DMAENABLE_CLR_EN_1_MASK   (0x00000002U)
 
#define ADC_DMAENABLE_CLR_EN_1_ENABLED   (1U)
 
#define ADC_DMAENABLE_CLR_EN_1_DISABLED   (0U)
 
#define ADC_DMAENABLE_CLR_EN_1_DISABLE   (1U)
 
#define ADC_DMAENABLE_CLR_EN_1_NO_ACTION   (0U)
 
#define ADC_DMAENABLE_CLR_EN_0_SHIFT   (0U)
 
#define ADC_DMAENABLE_CLR_EN_0_MASK   (0x00000001U)
 
#define ADC_DMAENABLE_CLR_EN_0_ENABLED   (1U)
 
#define ADC_DMAENABLE_CLR_EN_0_DISABLED   (0U)
 
#define ADC_DMAENABLE_CLR_EN_0_DISABLE   (1U)
 
#define ADC_DMAENABLE_CLR_EN_0_NO_ACTION   (0U)
 
#define ADC_CTRL_STEP_ID_TAG_SHIFT   (1U)
 
#define ADC_CTRL_STEP_ID_TAG_MASK   (0x00000002U)
 
#define ADC_CTRL_STEP_ID_TAG_WRZERO   (0U)
 
#define ADC_CTRL_STEP_ID_TAG_CHANNELID   (1U)
 
#define ADC_CTRL_EN_SHIFT   (0U)
 
#define ADC_CTRL_EN_MASK   (0x00000001U)
 
#define ADC_CTRL_EN_DISABLE   (0U)
 
#define ADC_CTRL_EN_ENABLE   (1U)
 
#define ADC_CTRL_POWER_DOWN_SHIFT   (4U)
 
#define ADC_CTRL_POWER_DOWN_MASK   (0x00000010U)
 
#define ADC_CTRL_POWER_DOWN_AFEPOWERUP   (0U)
 
#define ADC_CTRL_POWER_DOWN_AFEPOWERDOWN   (1U)
 
#define ADC_CTRL_HW_PREEMPT_SHIFT   (9U)
 
#define ADC_CTRL_HW_PREEMPT_MASK   (0x00000200U)
 
#define ADC_CTRL_HW_PREEMPT_NOPREEMPT   (0U)
 
#define ADC_CTRL_HW_PREEMPT   (1U)
 
#define ADC_CTRL_AFE_PEN_SHIFT   (5U)
 
#define ADC_CTRL_AFE_PEN_MASK   (0x00000060U)
 
#define ADC_CTRL_RESERVED0_SHIFT   (10U)
 
#define ADC_CTRL_RESERVED0_MASK   (0xfffffc00U)
 
#define ADC_CTRL_TOUCH_SCREEN_EN_SHIFT   (7U)
 
#define ADC_CTRL_TOUCH_SCREEN_EN_MASK   (0x00000080U)
 
#define ADC_CTRL_TOUCH_SCREEN_EN_DISABLE   (0U)
 
#define ADC_CTRL_TOUCH_SCREEN_EN_ENABLE   (1U)
 
#define ADC_CTRL_HW_EVT_MAPPING_SHIFT   (8U)
 
#define ADC_CTRL_HW_EVT_MAPPING_MASK   (0x00000100U)
 
#define ADC_CTRL_HW_EVT_MAPPING_PENTOUCHIRQ   (0U)
 
#define ADC_CTRL_HW_EVT_MAPPING_HWEVTINPUT   (1U)
 
#define ADC_CTRL_BIAS_SELECT_SHIFT   (3U)
 
#define ADC_CTRL_BIAS_SELECT_MASK   (0x00000008U)
 
#define ADC_CTRL_BIAS_SELECT_INTERNAL   (0U)
 
#define ADC_CTRL_BIAS_SELECT_EXTERNAL   (1U)
 
#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_SHIFT   (2U)
 
#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_MASK   (0x00000004U)
 
#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_PROTECTED   (0U)
 
#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_NOTPROTECTED   (1U)
 
#define ADC_CTRL_HW_MID_EN_SHIFT   (10U)
 
#define ADC_CTRL_HW_MID_EN_MASK   (0x00000400U)
 
#define ADC_CTRL_HW_MID_EN_DISABLE   (0U)
 
#define ADC_CTRL_HW_MID_EN_ENABLE   (1U)
 
#define ADC_CTRL_HW_MID_SEL_SHIFT   (11U)
 
#define ADC_CTRL_HW_MID_SEL_MASK   (0x00000800U)
 
#define ADC_CTRL_HW_MID_SEL_DISABLE   (0U)
 
#define ADC_CTRL_HW_MID_SEL_ENABLE   (1U)
 
#define ADC_ADCSTAT_MEM_INIT_DONE_SHIFT   (6U)
 
#define ADC_ADCSTAT_MEM_INIT_DONE_MASK   (0x00000040U)
 
#define ADC_ADCSTAT_MEM_INIT_DONE_RESETVAL   (0U)
 
#define ADC_ADCSTAT_MEM_INIT_DONE   (1U)
 
#define ADC_ADCSTAT_RESERVED0_SHIFT   (9U)
 
#define ADC_ADCSTAT_RESERVED0_MASK   (0xfffffe00U)
 
#define ADC_ADCSTAT_AFE_BUSY_SHIFT   (8U)
 
#define ADC_ADCSTAT_AFE_BUSY_MASK   (0x00000100U)
 
#define ADC_ADCSTAT_AFE_BUSY_IDLE   (0U)
 
#define ADC_ADCSTAT_AFE_BUSY   (1U)
 
#define ADC_ADCSTAT_FSM_BUSY_SHIFT   (5U)
 
#define ADC_ADCSTAT_FSM_BUSY_MASK   (0x00000020U)
 
#define ADC_ADCSTAT_FSM_BUSY_IDLE   (0U)
 
#define ADC_ADCSTAT_FSM_BUSY   (1U)
 
#define ADC_ADCSTAT_STEP_ID_SHIFT   (0U)
 
#define ADC_ADCSTAT_STEP_ID_MASK   (0x0000001fU)
 
#define ADC_ADCSTAT_STEP_ID_STEP1   (0U)
 
#define ADC_ADCSTAT_STEP_ID_STEP2   (1U)
 
#define ADC_ADCSTAT_STEP_ID_STEP3   (2U)
 
#define ADC_ADCSTAT_STEP_ID_STEP4   (3U)
 
#define ADC_ADCSTAT_STEP_ID_STEP5   (4U)
 
#define ADC_ADCSTAT_STEP_ID_STEP6   (5U)
 
#define ADC_ADCSTAT_STEP_ID_STEP7   (6U)
 
#define ADC_ADCSTAT_STEP_ID_STEP8   (7U)
 
#define ADC_ADCSTAT_STEP_ID_STEP9   (8U)
 
#define ADC_ADCSTAT_STEP_ID_STEP10   (9U)
 
#define ADC_ADCSTAT_STEP_ID_STEP11   (10U)
 
#define ADC_ADCSTAT_STEP_ID_STEP12   (11U)
 
#define ADC_ADCSTAT_STEP_ID_STEP13   (12U)
 
#define ADC_ADCSTAT_STEP_ID_STEP14   (13U)
 
#define ADC_ADCSTAT_STEP_ID_STEP15   (14U)
 
#define ADC_ADCSTAT_STEP_ID_STEP16   (15U)
 
#define ADC_ADCSTAT_STEP_ID_IDLE   (16U)
 
#define ADC_ADCSTAT_STEP_ID_CHARGE   (17U)
 
#define ADC_ADCSTAT_PEN_IRQ1_SHIFT   (7U)
 
#define ADC_ADCSTAT_PEN_IRQ1_MASK   (0x00000080U)
 
#define ADC_ADCRANGE_RESERVED1_SHIFT   (28U)
 
#define ADC_ADCRANGE_RESERVED1_MASK   (0xf0000000U)
 
#define ADC_ADCRANGE_HIGH_RANGE_DATA_SHIFT   (16U)
 
#define ADC_ADCRANGE_HIGH_RANGE_DATA_MASK   (0x0fff0000U)
 
#define ADC_ADCRANGE_LOW_RANGE_DATA_SHIFT   (0U)
 
#define ADC_ADCRANGE_LOW_RANGE_DATA_MASK   (0x00000fffU)
 
#define ADC_ADCRANGE_RESERVED0_SHIFT   (12U)
 
#define ADC_ADCRANGE_RESERVED0_MASK   (0x0000f000U)
 
#define ADC_MISC_AFE_SPARE_INPUT_SHIFT   (0U)
 
#define ADC_MISC_AFE_SPARE_INPUT_MASK   (0x0000000fU)
 
#define ADC_MISC_RESERVED0_SHIFT   (8U)
 
#define ADC_MISC_RESERVED0_MASK   (0xffffff00U)
 
#define ADC_MISC_AFE_SPARE_OUTPUT_SHIFT   (8U)
 
#define ADC_MISC_AFE_SPARE_OUTPUT_MASK   (0x00000f00U)
 
#define ADC_STEPENABLE_STEP_SHIFT   (1U)
 
#define ADC_STEPENABLE_STEP_MASK   (0x0001FFFEU)
 
#define ADC_STEPENABLE_STEP3_SHIFT   (3U)
 
#define ADC_STEPENABLE_STEP3_MASK   (0x00000008U)
 
#define ADC_STEPENABLE_STEP8_SHIFT   (8U)
 
#define ADC_STEPENABLE_STEP8_MASK   (0x00000100U)
 
#define ADC_STEPENABLE_STEP2_SHIFT   (2U)
 
#define ADC_STEPENABLE_STEP2_MASK   (0x00000004U)
 
#define ADC_STEPENABLE_STEP16_SHIFT   (16U)
 
#define ADC_STEPENABLE_STEP16_MASK   (0x00010000U)
 
#define ADC_STEPENABLE_STEP15_SHIFT   (15U)
 
#define ADC_STEPENABLE_STEP15_MASK   (0x00008000U)
 
#define ADC_STEPENABLE_STEP12_SHIFT   (12U)
 
#define ADC_STEPENABLE_STEP12_MASK   (0x00001000U)
 
#define ADC_STEPENABLE_STEP13_SHIFT   (13U)
 
#define ADC_STEPENABLE_STEP13_MASK   (0x00002000U)
 
#define ADC_STEPENABLE_RESERVED0_SHIFT   (17U)
 
#define ADC_STEPENABLE_RESERVED0_MASK   (0xfffe0000U)
 
#define ADC_STEPENABLE_STEP14_SHIFT   (14U)
 
#define ADC_STEPENABLE_STEP14_MASK   (0x00004000U)
 
#define ADC_STEPENABLE_STEP7_SHIFT   (7U)
 
#define ADC_STEPENABLE_STEP7_MASK   (0x00000080U)
 
#define ADC_STEPENABLE_STEP9_SHIFT   (9U)
 
#define ADC_STEPENABLE_STEP9_MASK   (0x00000200U)
 
#define ADC_STEPENABLE_STEP10_SHIFT   (10U)
 
#define ADC_STEPENABLE_STEP10_MASK   (0x00000400U)
 
#define ADC_STEPENABLE_STEP4_SHIFT   (4U)
 
#define ADC_STEPENABLE_STEP4_MASK   (0x00000010U)
 
#define ADC_STEPENABLE_STEP1_SHIFT   (1U)
 
#define ADC_STEPENABLE_STEP1_MASK   (0x00000002U)
 
#define ADC_STEPENABLE_STEP5_SHIFT   (5U)
 
#define ADC_STEPENABLE_STEP5_MASK   (0x00000020U)
 
#define ADC_STEPENABLE_STEP11_SHIFT   (11U)
 
#define ADC_STEPENABLE_STEP11_MASK   (0x00000800U)
 
#define ADC_STEPENABLE_STEP6_SHIFT   (6U)
 
#define ADC_STEPENABLE_STEP6_MASK   (0x00000040U)
 
#define ADC_STEPENABLE_TS_CHARGE_SHIFT   (0U)
 
#define ADC_STEPENABLE_TS_CHARGE_MASK   (0x00000001U)
 
#define ADC_IDLECONFIG_XPPSW_SWC_SHIFT   (5U)
 
#define ADC_IDLECONFIG_XPPSW_SWC_MASK   (0x00000020U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_SHIFT   (12U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_MASK   (0x00007000U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_VDDA   (0U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_XPUL   (1U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_YPLL   (2U)
 
#define ADC_IDLECONFIG_SEL_RFP_SWC_VREFP   (3U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_SHIFT   (15U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_MASK   (0x00078000U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_1   (0U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_2   (1U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_3   (2U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_4   (3U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_5   (4U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_6   (5U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_7   (6U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_8   (7U)
 
#define ADC_IDLECONFIG_SEL_INM_SWM_VREFN   (8U)
 
#define ADC_IDLECONFIG_RESERVED0_SHIFT   (0U)
 
#define ADC_IDLECONFIG_RESERVED0_MASK   (0x0000001fU)
 
#define ADC_IDLECONFIG_YPPSW_SWC_SHIFT   (7U)
 
#define ADC_IDLECONFIG_YPPSW_SWC_MASK   (0x00000080U)
 
#define ADC_IDLECONFIG_YPNSW_SWC_SHIFT   (10U)
 
#define ADC_IDLECONFIG_YPNSW_SWC_MASK   (0x00000400U)
 
#define ADC_IDLECONFIG_RESERVED1_SHIFT   (26U)
 
#define ADC_IDLECONFIG_RESERVED1_MASK   (0xfc000000U)
 
#define ADC_IDLECONFIG_XNNSW_SWC_SHIFT   (6U)
 
#define ADC_IDLECONFIG_XNNSW_SWC_MASK   (0x00000040U)
 
#define ADC_IDLECONFIG_XNPSW_SWC_SHIFT   (9U)
 
#define ADC_IDLECONFIG_XNPSW_SWC_MASK   (0x00000200U)
 
#define ADC_IDLECONFIG_YNNSW_SWC_SHIFT   (8U)
 
#define ADC_IDLECONFIG_YNNSW_SWC_MASK   (0x00000100U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_SHIFT   (23U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_MASK   (0x01800000U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_VSSA   (0U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_XNUR   (1U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_YNLR   (2U)
 
#define ADC_IDLECONFIG_SEL_RFM_SWC_VREFN   (3U)
 
#define ADC_IDLECONFIG_WPNSW_SWC_SHIFT   (11U)
 
#define ADC_IDLECONFIG_WPNSW_SWC_MASK   (0x00000800U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_SHIFT   (19U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_MASK   (0x00780000U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_1   (0U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_2   (1U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_3   (2U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_4   (3U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_5   (4U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_6   (5U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_7   (6U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_8   (7U)
 
#define ADC_IDLECONFIG_SEL_INP_SWC_VREFN   (8U)
 
#define ADC_IDLECONFIG_DIFF_CNTRL_SHIFT   (25U)
 
#define ADC_IDLECONFIG_DIFF_CNTRL_MASK   (0x02000000U)
 
#define ADC_IDLECONFIG_DIFF_CNTRL_SINGLE   (0U)
 
#define ADC_IDLECONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SHIFT   (25U)
 
#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_MASK   (0x02000000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SINGLE   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_SHIFT   (9U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_MASK   (0x00000200U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_SHIFT   (10U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_MASK   (0x00000400U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_SHIFT   (5U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_MASK   (0x00000020U)
 
#define ADC_TS_CHARGE_STEPCONFIG_RESERVED0_SHIFT   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_RESERVED0_MASK   (0x0000001fU)
 
#define ADC_TS_CHARGE_STEPCONFIG_RESERVED1_SHIFT   (26U)
 
#define ADC_TS_CHARGE_STEPCONFIG_RESERVED1_MASK   (0xfc000000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_SHIFT   (15U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_MASK   (0x00078000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_1   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_2   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_3   (2U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_4   (3U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_5   (4U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_6   (5U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_7   (6U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_8   (7U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_VREFN   (8U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_SHIFT   (12U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_MASK   (0x00007000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VDDA   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_XPUL   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_YPLL   (2U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VREFP   (3U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_INTREF   (4U)
 
#define ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_SHIFT   (11U)
 
#define ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_MASK   (0x00000800U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_SHIFT   (19U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_MASK   (0x00780000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_1   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_2   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_3   (2U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_4   (3U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_5   (4U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_6   (5U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_7   (6U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_8   (7U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_VREFN   (8U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_SHIFT   (23U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_MASK   (0x01800000U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VSSA   (0U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_XNUR   (1U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_YNLR   (2U)
 
#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VREFN   (3U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_SHIFT   (7U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_MASK   (0x00000080U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_SHIFT   (6U)
 
#define ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_MASK   (0x00000040U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_SHIFT   (8U)
 
#define ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_MASK   (0x00000100U)
 
#define ADC_TS_CHARGE_DELAY_OPENDELAY_SHIFT   (0U)
 
#define ADC_TS_CHARGE_DELAY_OPENDELAY_MASK   (0x0003ffffU)
 
#define ADC_TS_CHARGE_DELAY_RESERVED0_SHIFT   (18U)
 
#define ADC_TS_CHARGE_DELAY_RESERVED0_MASK   (0xfffc0000U)
 
#define ADC_IRQ_EOI_LINE_NUMBER_SHIFT   (0U)
 
#define ADC_IRQ_EOI_LINE_NUMBER_MASK   (0x00000001U)
 
#define ADC_IRQ_EOI_LINE_NUMBER_EOI   (0U)
 
#define ADC_IRQ_EOI_RESERVED0_SHIFT   (1U)
 
#define ADC_IRQ_EOI_RESERVED0_MASK   (0x7ffffffeU)
 
#define ADC_STEPCONFIG_YNNSW_SWC_SHIFT   (8U)
 
#define ADC_STEPCONFIG_YNNSW_SWC_MASK   (0x00000100U)
 
#define ADC_STEPCONFIG_DIFF_CNTRL_SHIFT   (25U)
 
#define ADC_STEPCONFIG_DIFF_CNTRL_MASK   (0x02000000U)
 
#define ADC_STEPCONFIG_DIFF_CNTRL_SINGLE   (0U)
 
#define ADC_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)
 
#define ADC_STEPCONFIG_WPNSW_SWC_SHIFT   (11U)
 
#define ADC_STEPCONFIG_WPNSW_SWC_MASK   (0x00000800U)
 
#define ADC_STEPCONFIG_MODE_SHIFT   (0U)
 
#define ADC_STEPCONFIG_MODE_MASK   (0x00000003U)
 
#define ADC_STEPCONFIG_MODE_SW_EN_ONESHOT   (0U)
 
#define ADC_STEPCONFIG_MODE_SW_EN_CONTINUOUS   (1U)
 
#define ADC_STEPCONFIG_MODE_HW_SYNC_ONESHOT   (2U)
 
#define ADC_STEPCONFIG_MODE_HW_SYNC_CONTINUOUS   (3U)
 
#define ADC_STEPCONFIG_AVERAGING_SHIFT   (2U)
 
#define ADC_STEPCONFIG_AVERAGING_MASK   (0x0000001cU)
 
#define ADC_STEPCONFIG_AVERAGING_NOAVG   (0U)
 
#define ADC_STEPCONFIG_AVERAGING_2_SAMPLESAVG   (1U)
 
#define ADC_STEPCONFIG_AVERAGING_4_SAMPLESAVG   (2U)
 
#define ADC_STEPCONFIG_AVERAGING_8_SAMPLESAVG   (3U)
 
#define ADC_STEPCONFIG_AVERAGING_16_SAMPLESAV   (4U)
 
#define ADC_STEPCONFIG_XPPSW_SWC_SHIFT   (5U)
 
#define ADC_STEPCONFIG_XPPSW_SWC_MASK   (0x00000020U)
 
#define ADC_STEPCONFIG_YPPSW_SWC_SHIFT   (7U)
 
#define ADC_STEPCONFIG_YPPSW_SWC_MASK   (0x00000080U)
 
#define ADC_STEPCONFIG_XNNSW_SWC_SHIFT   (6U)
 
#define ADC_STEPCONFIG_XNNSW_SWC_MASK   (0x00000040U)
 
#define ADC_STEPCONFIG_FIFO_SELECT_SHIFT   (26U)
 
#define ADC_STEPCONFIG_FIFO_SELECT_MASK   (0x04000000U)
 
#define ADC_STEPCONFIG_FIFO_SELECT_0   (0U)
 
#define ADC_STEPCONFIG_FIFO_SELECT_1   (1U)
 
#define ADC_STEPCONFIG_RESERVED0_SHIFT   (28U)
 
#define ADC_STEPCONFIG_RESERVED0_MASK   (0xf0000000U)
 
#define ADC_STEPCONFIG_RANGE_CHECK_SHIFT   (27U)
 
#define ADC_STEPCONFIG_RANGE_CHECK_MASK   (0x08000000U)
 
#define ADC_STEPCONFIG_RANGE_CHECK_DISABLE   (0U)
 
#define ADC_STEPCONFIG_RANGE_CHECK_ENABLE   (1U)
 
#define ADC_STEPCONFIG_YPNSW_SWC_SHIFT   (10U)
 
#define ADC_STEPCONFIG_YPNSW_SWC_MASK   (0x00000400U)
 
#define ADC_STEPCONFIG_XNPSW_SWC_SHIFT   (9U)
 
#define ADC_STEPCONFIG_XNPSW_SWC_MASK   (0x00000200U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_SHIFT   (12U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_MASK   (0x00007000U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_VDDA   (0U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_XPUL   (1U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_YPLL   (2U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_VREFP   (3U)
 
#define ADC_STEPCONFIG_SEL_RFP_SWC_INTREF   (4U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_SHIFT   (15U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_MASK   (0x00078000U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_1   (0U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_2   (1U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_3   (2U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_4   (3U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_5   (4U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_6   (5U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_7   (6U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_8   (7U)
 
#define ADC_STEPCONFIG_SEL_INM_SWC_VREFN   (8U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_SHIFT   (19U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_MASK   (0x00780000U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_1   (0U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_2   (1U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_3   (2U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_4   (3U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_5   (4U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_6   (5U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_7   (6U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_8   (7U)
 
#define ADC_STEPCONFIG_SEL_INP_SWC_VREFN   (8U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_SHIFT   (23U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_MASK   (0x01800000U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_VSSA   (0U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_XNUR   (1U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_YNLR   (2U)
 
#define ADC_STEPCONFIG_SEL_RFM_SWC_VREFN   (3U)
 
#define ADC_STEPDELAY_RESERVED0_SHIFT   (18U)
 
#define ADC_STEPDELAY_RESERVED0_MASK   (0x00fc0000U)
 
#define ADC_STEPDELAY_OPENDELAY_SHIFT   (0U)
 
#define ADC_STEPDELAY_OPENDELAY_MASK   (0x0003ffffU)
 
#define ADC_STEPDELAY_SAMPLEDELAY_SHIFT   (24U)
 
#define ADC_STEPDELAY_SAMPLEDELAY_MASK   (0xff000000U)
 
#define ADC_FIFOCOUNT_WORDS_IN_FIFO_SHIFT   (0U)
 
#define ADC_FIFOCOUNT_WORDS_IN_FIFO_MASK   (0x000001ffU)
 
#define ADC_FIFOCOUNT_RESERVED0_SHIFT   (7U)
 
#define ADC_FIFOCOUNT_RESERVED0_MASK   (0xffffff80U)
 
#define ADC_FIFOTHRESHOLD_RESERVED0_SHIFT   (6U)
 
#define ADC_FIFOTHRESHOLD_RESERVED0_MASK   (0xffffffc0U)
 
#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_SHIFT   (0U)
 
#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MASK   (0x000000ffU)
 
#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MAX   (256U)
 
#define ADC_DMAREQ_DMA_REQUEST_LEVEL_SHIFT   (0U)
 
#define ADC_DMAREQ_DMA_REQUEST_LEVEL_MASK   (0x0000003fU)
 
#define ADC_DMAREQ_RESERVED0_SHIFT   (6U)
 
#define ADC_DMAREQ_RESERVED0_MASK   (0xffffffc0U)
 
#define ADC_FIFODATA_RESERVED1_SHIFT   (20U)
 
#define ADC_FIFODATA_RESERVED1_MASK   (0xfff00000U)
 
#define ADC_FIFODATA_ADCCHNLID_SHIFT   (16U)
 
#define ADC_FIFODATA_ADCCHNLID_MASK   (0x000f0000U)
 
#define ADC_FIFODATA_ADCDATA_SHIFT   (0U)
 
#define ADC_FIFODATA_ADCDATA_MASK   (0x00000fffU)
 
#define ADC_FIFODATA_RESERVED0_SHIFT   (12U)
 
#define ADC_FIFODATA_RESERVED0_MASK   (0x0000f000U)
 
#define ADC_SYSCONFIG_IDLEMODE_SHIFT   (2U)
 
#define ADC_SYSCONFIG_IDLEMODE_MASK   (0x0000000cU)
 
#define ADC_SYSCONFIG_IDLEMODE_FORCE   (0U)
 
#define ADC_SYSCONFIG_IDLEMODE_NO_IDLE   (1U)
 
#define ADC_SYSCONFIG_IDLEMODE_SMART_IDLE   (2U)
 
#define ADC_SYSCONFIG_IDLEMODE_SMART_IDLE_WAKEUP   (3U)
 
#define ADC_SYSCONFIG_RESERVED1_SHIFT   (4U)
 
#define ADC_SYSCONFIG_RESERVED1_MASK   (0xfffffff0U)
 
#define ADC_SYSCONFIG_RESERVED0_SHIFT   (0U)
 
#define ADC_SYSCONFIG_RESERVED0_MASK   (0x00000003U)
 

Macro Definition Documentation

◆ ADC_REVISION

#define ADC_REVISION   (0x0U)

◆ ADC_SYSCONFIG

#define ADC_SYSCONFIG   (0x10U)

◆ ADC_IRQSTATUS_RAW

#define ADC_IRQSTATUS_RAW   (0x24U)

◆ ADC_IRQSTATUS

#define ADC_IRQSTATUS   (0x28U)

◆ ADC_IRQENABLE_SET

#define ADC_IRQENABLE_SET   (0x2cU)

◆ ADC_IRQENABLE_CLR

#define ADC_IRQENABLE_CLR   (0x30U)

◆ ADC_IRQWAKEUP

#define ADC_IRQWAKEUP   (0x34U)

◆ ADC_DMAENABLE_SET

#define ADC_DMAENABLE_SET   (0x38U)

◆ ADC_DMAENABLE_CLR

#define ADC_DMAENABLE_CLR   (0x3cU)

◆ ADC_CTRL

#define ADC_CTRL   (0x40U)

◆ ADC_ADCSTAT

#define ADC_ADCSTAT   (0x44U)

◆ ADC_ADCRANGE

#define ADC_ADCRANGE   (0x48U)

◆ ADC_CLKDIV

#define ADC_CLKDIV   (0x4cU)

◆ ADC_MISC

#define ADC_MISC   (0x50U)

◆ ADC_STEPENABLE

#define ADC_STEPENABLE   (0x54U)

◆ ADC_IDLECONFIG

#define ADC_IDLECONFIG   (0x58U)

◆ ADC_TS_CHARGE_STEPCONFIG

#define ADC_TS_CHARGE_STEPCONFIG   (0x5cU)

◆ ADC_TS_CHARGE_DELAY

#define ADC_TS_CHARGE_DELAY   (0x60U)

◆ ADC_IRQ_EOI

#define ADC_IRQ_EOI   (0x20U)

◆ ADC_STEPCONFIG

#define ADC_STEPCONFIG (   m)    ((uint32_t)0x64U + ((m) * 0x8U))

◆ ADC_STEPCONFIG_NUM_ELEMS

#define ADC_STEPCONFIG_NUM_ELEMS   (16U)

◆ ADC_STEPDELAY

#define ADC_STEPDELAY (   m)    ((uint32_t)0x68U + ((m) * 0x8U))

◆ ADC_STEPDELAY_NUM_ELEMS

#define ADC_STEPDELAY_NUM_ELEMS   (16U)

◆ ADC_FIFOCOUNT

#define ADC_FIFOCOUNT (   m)    ((uint32_t)0xe4U + ((m) * 0xcU))

◆ ADC_FIFOCOUNT_NUM_ELEMS

#define ADC_FIFOCOUNT_NUM_ELEMS   (2U)

◆ ADC_FIFOTHRESHOLD

#define ADC_FIFOTHRESHOLD (   m)    ((uint32_t)0xe8U + ((m) * 0xcU))

◆ ADC_FIFOTHRESHOLD_NUM_ELEMS

#define ADC_FIFOTHRESHOLD_NUM_ELEMS   (2U)

◆ ADC_DMAREQ

#define ADC_DMAREQ (   m)    ((uint32_t)0xecU + ((m) * 0xcU))

◆ ADC_DMAREQ_NUM_ELEMS

#define ADC_DMAREQ_NUM_ELEMS   (2U)

◆ ADC_FIFODATA

#define ADC_FIFODATA (   m)    ((uint32_t)0x100U + ((m) * 0x100U))

◆ ADC_FIFODATA_NUM_ELEMS

#define ADC_FIFODATA_NUM_ELEMS   (2U)

◆ ADC_REVISION_X_MAJOR_SHIFT

#define ADC_REVISION_X_MAJOR_SHIFT   (8U)

◆ ADC_REVISION_X_MAJOR_MASK

#define ADC_REVISION_X_MAJOR_MASK   (0x00000700U)

◆ ADC_REVISION_FUNC_SHIFT

#define ADC_REVISION_FUNC_SHIFT   (16U)

◆ ADC_REVISION_FUNC_MASK

#define ADC_REVISION_FUNC_MASK   (0x0fff0000U)

◆ ADC_REVISION_R_RTL_SHIFT

#define ADC_REVISION_R_RTL_SHIFT   (11U)

◆ ADC_REVISION_R_RTL_MASK

#define ADC_REVISION_R_RTL_MASK   (0x0000f800U)

◆ ADC_REVISION_RESERVED0_SHIFT

#define ADC_REVISION_RESERVED0_SHIFT   (28U)

◆ ADC_REVISION_RESERVED0_MASK

#define ADC_REVISION_RESERVED0_MASK   (0x30000000U)

◆ ADC_REVISION_SCHEME_SHIFT

#define ADC_REVISION_SCHEME_SHIFT   (30U)

◆ ADC_REVISION_SCHEME_MASK

#define ADC_REVISION_SCHEME_MASK   (0xc0000000U)

◆ ADC_REVISION_CUSTOM_SHIFT

#define ADC_REVISION_CUSTOM_SHIFT   (6U)

◆ ADC_REVISION_CUSTOM_MASK

#define ADC_REVISION_CUSTOM_MASK   (0x000000c0U)

◆ ADC_REVISION_Y_MINOR_SHIFT

#define ADC_REVISION_Y_MINOR_SHIFT   (0U)

◆ ADC_REVISION_Y_MINOR_MASK

#define ADC_REVISION_Y_MINOR_MASK   (0x0000003fU)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO0_THR_SHIFT   (2U)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_MASK

#define ADC_IRQSTATUS_RAW_FIFO0_THR_MASK   (0x00000004U)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_THR_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_THR_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO0_THR_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_THR_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO0_THR_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SHIFT   (7U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_MASK

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_MASK   (0x00000080U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO1_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SHIFT

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SHIFT   (1U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_MASK

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_MASK   (0x00000002U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_EVT_PEND

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SET_EVT

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_ACTION

#define ADC_IRQSTATUS_RAW_END_OF_SEQUENCE_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SHIFT

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SHIFT   (0U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_MASK

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_MASK   (0x00000001U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_EVT_PEND

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SET_EVT

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_ACTION

#define ADC_IRQSTATUS_RAW_AFE_EOC_MISSING_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_RESERVED0_SHIFT

#define ADC_IRQSTATUS_RAW_RESERVED0_SHIFT   (11U)

◆ ADC_IRQSTATUS_RAW_RESERVED0_MASK

#define ADC_IRQSTATUS_RAW_RESERVED0_MASK   (0xfffff800U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SHIFT

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_MASK

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_PEND

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SET

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_SET   (1U)

◆ ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION

#define ADC_IRQSTATUS_RAW_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SHIFT   (6U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_MASK

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_MASK   (0x00000040U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO1_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SHIFT   (4U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_MASK

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_MASK   (0x00000010U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO0_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SHIFT   (3U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_MASK

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_MASK   (0x00000008U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO0_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SHIFT

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SHIFT   (8U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_MASK

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_MASK   (0x00000100U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_EVT_PEND

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SET_EVT

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_ACTION

#define ADC_IRQSTATUS_RAW_OUT_OF_RANGE_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SHIFT

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SHIFT   (10U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_MASK

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_MASK   (0x00000400U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_EVT_PEND

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SET_EVT

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_ACTION

#define ADC_IRQSTATUS_RAW_PEN_IRQ_SYNCHRONIZED_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_SHIFT

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_SHIFT   (9U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_MASK

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_MASK   (0x00000200U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_PEND

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_PEND

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_SET

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_SET   (1U)

◆ ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_ACTION

#define ADC_IRQSTATUS_RAW_PEN_UP_EVT_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_SHIFT

#define ADC_IRQSTATUS_RAW_FIFO1_THR_SHIFT   (5U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_MASK

#define ADC_IRQSTATUS_RAW_FIFO1_THR_MASK   (0x00000020U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_THR_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_NO_EVT_PEND

#define ADC_IRQSTATUS_RAW_FIFO1_THR_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_SET_EVT

#define ADC_IRQSTATUS_RAW_FIFO1_THR_SET_EVT   (1U)

◆ ADC_IRQSTATUS_RAW_FIFO1_THR_NO_ACTION

#define ADC_IRQSTATUS_RAW_FIFO1_THR_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_RESERVED0_SHIFT

#define ADC_IRQSTATUS_RESERVED0_SHIFT   (11U)

◆ ADC_IRQSTATUS_RESERVED0_MASK

#define ADC_IRQSTATUS_RESERVED0_MASK   (0xfffff800U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_SHIFT

#define ADC_IRQSTATUS_END_OF_SEQUENCE_SHIFT   (1U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_MASK

#define ADC_IRQSTATUS_END_OF_SEQUENCE_MASK   (0x00000002U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_EVT_PEND

#define ADC_IRQSTATUS_END_OF_SEQUENCE_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_NO_EVT_PEND

#define ADC_IRQSTATUS_END_OF_SEQUENCE_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_CLR_EVT

#define ADC_IRQSTATUS_END_OF_SEQUENCE_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_END_OF_SEQUENCE_NO_ACTION

#define ADC_IRQSTATUS_END_OF_SEQUENCE_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_SHIFT

#define ADC_IRQSTATUS_AFE_EOC_MISSING_SHIFT   (0U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_MASK

#define ADC_IRQSTATUS_AFE_EOC_MISSING_MASK   (0x00000001U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_EVT_PEND

#define ADC_IRQSTATUS_AFE_EOC_MISSING_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_NO_EVT_PEND

#define ADC_IRQSTATUS_AFE_EOC_MISSING_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_SET_EVT

#define ADC_IRQSTATUS_AFE_EOC_MISSING_SET_EVT   (1U)

◆ ADC_IRQSTATUS_AFE_EOC_MISSING_NO_ACTION

#define ADC_IRQSTATUS_AFE_EOC_MISSING_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_SHIFT

#define ADC_IRQSTATUS_PEN_UP_EVT_SHIFT   (9U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_MASK

#define ADC_IRQSTATUS_PEN_UP_EVT_MASK   (0x00000200U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_PEND

#define ADC_IRQSTATUS_PEN_UP_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_NO_PEND

#define ADC_IRQSTATUS_PEN_UP_EVT_NO_PEND   (0U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_CLR

#define ADC_IRQSTATUS_PEN_UP_EVT_CLR   (1U)

◆ ADC_IRQSTATUS_PEN_UP_EVT_NO_ACTION

#define ADC_IRQSTATUS_PEN_UP_EVT_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_SHIFT

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_SHIFT   (7U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_MASK

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_MASK   (0x00000080U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_CLR_EVT

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_ACTION

#define ADC_IRQSTATUS_FIFO1_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO1_THR_SHIFT

#define ADC_IRQSTATUS_FIFO1_THR_SHIFT   (5U)

◆ ADC_IRQSTATUS_FIFO1_THR_MASK

#define ADC_IRQSTATUS_FIFO1_THR_MASK   (0x00000020U)

◆ ADC_IRQSTATUS_FIFO1_THR_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_THR_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO1_THR_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_THR_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO1_THR_CLR_EVT

#define ADC_IRQSTATUS_FIFO1_THR_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO1_THR_NO_ACTION

#define ADC_IRQSTATUS_FIFO1_THR_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_SHIFT

#define ADC_IRQSTATUS_FIFO1_OVERRUN_SHIFT   (6U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_MASK

#define ADC_IRQSTATUS_FIFO1_OVERRUN_MASK   (0x00000040U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_OVERRUN_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO1_OVERRUN_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_CLR_EVT

#define ADC_IRQSTATUS_FIFO1_OVERRUN_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO1_OVERRUN_NO_ACTION

#define ADC_IRQSTATUS_FIFO1_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_SHIFT

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_SHIFT   (4U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_MASK

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_MASK   (0x00000010U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_CLR_EVT

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_ACTION

#define ADC_IRQSTATUS_FIFO0_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_SHIFT

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_MASK

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_PEND

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_PEND   (1U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_PEND   (0U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_CLR

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_CLR   (1U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION

#define ADC_IRQSTATUS_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_SHIFT

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_MASK

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_PEND

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_PEND   (1U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_PEND

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_PEND   (0U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_CLR

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_CLR   (1U)

◆ ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION

#define ADC_IRQSTATUS_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_SHIFT

#define ADC_IRQSTATUS_FIFO0_OVERRUN_SHIFT   (3U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_MASK

#define ADC_IRQSTATUS_FIFO0_OVERRUN_MASK   (0x00000008U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_OVERRUN_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_OVERRUN_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_CLR_EVT

#define ADC_IRQSTATUS_FIFO0_OVERRUN_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO0_OVERRUN_NO_ACTION

#define ADC_IRQSTATUS_FIFO0_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_SHIFT

#define ADC_IRQSTATUS_OUT_OF_RANGE_SHIFT   (8U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_MASK

#define ADC_IRQSTATUS_OUT_OF_RANGE_MASK   (0x00000100U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_EVT_PEND

#define ADC_IRQSTATUS_OUT_OF_RANGE_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_NO_EVT_PEND

#define ADC_IRQSTATUS_OUT_OF_RANGE_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_CLR_EVT

#define ADC_IRQSTATUS_OUT_OF_RANGE_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_OUT_OF_RANGE_NO_ACTION

#define ADC_IRQSTATUS_OUT_OF_RANGE_NO_ACTION   (0U)

◆ ADC_IRQSTATUS_FIFO0_THR_SHIFT

#define ADC_IRQSTATUS_FIFO0_THR_SHIFT   (2U)

◆ ADC_IRQSTATUS_FIFO0_THR_MASK

#define ADC_IRQSTATUS_FIFO0_THR_MASK   (0x00000004U)

◆ ADC_IRQSTATUS_FIFO0_THR_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_THR_EVT_PEND   (1U)

◆ ADC_IRQSTATUS_FIFO0_THR_NO_EVT_PEND

#define ADC_IRQSTATUS_FIFO0_THR_NO_EVT_PEND   (0U)

◆ ADC_IRQSTATUS_FIFO0_THR_CLR_EVT

#define ADC_IRQSTATUS_FIFO0_THR_CLR_EVT   (1U)

◆ ADC_IRQSTATUS_FIFO0_THR_NO_ACTION

#define ADC_IRQSTATUS_FIFO0_THR_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_SHIFT

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_MASK

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLED

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_DISABLED

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLE

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION

#define ADC_IRQENABLE_SET_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_SHIFT

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_SHIFT   (4U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_MASK

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_MASK   (0x00000010U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLED

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_DISABLED

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLE

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_SHIFT

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_SHIFT   (6U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_MASK

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_MASK   (0x00000040U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLED

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_DISABLED

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLE

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_OVERRUN_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO1_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_SHIFT

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_SHIFT   (3U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_MASK

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_MASK   (0x00000008U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLED

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_DISABLED

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLE

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_OVERRUN_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO0_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_SHIFT

#define ADC_IRQENABLE_SET_FIFO1_THR_SHIFT   (5U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_MASK

#define ADC_IRQENABLE_SET_FIFO1_THR_MASK   (0x00000020U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_ENABLED

#define ADC_IRQENABLE_SET_FIFO1_THR_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_DISABLED

#define ADC_IRQENABLE_SET_FIFO1_THR_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_ENABLE

#define ADC_IRQENABLE_SET_FIFO1_THR_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_THR_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO1_THR_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_SHIFT

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_SHIFT   (7U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_MASK

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_MASK   (0x00000080U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLED

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_DISABLED

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLE

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_SHIFT

#define ADC_IRQENABLE_SET_FIFO0_THR_SHIFT   (2U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_MASK

#define ADC_IRQENABLE_SET_FIFO0_THR_MASK   (0x00000004U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_ENABLED

#define ADC_IRQENABLE_SET_FIFO0_THR_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_DISABLED

#define ADC_IRQENABLE_SET_FIFO0_THR_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_ENABLE

#define ADC_IRQENABLE_SET_FIFO0_THR_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_FIFO0_THR_NO_ACTION

#define ADC_IRQENABLE_SET_FIFO0_THR_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_RESERVED0_SHIFT

#define ADC_IRQENABLE_SET_RESERVED0_SHIFT   (11U)

◆ ADC_IRQENABLE_SET_RESERVED0_MASK

#define ADC_IRQENABLE_SET_RESERVED0_MASK   (0xfffff800U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_SHIFT

#define ADC_IRQENABLE_SET_PEN_UP_EVT_SHIFT   (9U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_MASK

#define ADC_IRQENABLE_SET_PEN_UP_EVT_MASK   (0x00000200U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLED

#define ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_DISABLED

#define ADC_IRQENABLE_SET_PEN_UP_EVT_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLE

#define ADC_IRQENABLE_SET_PEN_UP_EVT_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_PEN_UP_EVT_NO_ACTION

#define ADC_IRQENABLE_SET_PEN_UP_EVT_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_SHIFT

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_SHIFT   (1U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_MASK

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_MASK   (0x00000002U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLED

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_DISABLED

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLE

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_END_OF_SEQUENCE_NO_ACTION

#define ADC_IRQENABLE_SET_END_OF_SEQUENCE_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_SHIFT

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_SHIFT   (0U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_MASK

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_MASK   (0x00000001U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_EVT_PEND

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_EVT_PEND   (1U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_EVT_PEND

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_EVT_PEND   (0U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_SET_EVT

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_SET_EVT   (1U)

◆ ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_ACTION

#define ADC_IRQENABLE_SET_AFE_EOC_MISSING_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_SHIFT

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_SHIFT   (8U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_MASK

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_MASK   (0x00000100U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLED

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_DISABLED

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLE

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_OUT_OF_RANGE_NO_ACTION

#define ADC_IRQENABLE_SET_OUT_OF_RANGE_NO_ACTION   (0U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_SHIFT

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_MASK

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLED

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLED   (1U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_DISABLED

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_DISABLED   (0U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLE

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_ENABLE   (1U)

◆ ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION

#define ADC_IRQENABLE_SET_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_SHIFT

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_SHIFT   (3U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_MASK

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_MASK   (0x00000008U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_ENABLED

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLED

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLE

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_OVERRUN_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO0_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_SHIFT

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_SHIFT   (0U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_MASK

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_MASK   (0x00000001U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_ENABLED

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLED

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLE

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_ASYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_SHIFT

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_SHIFT   (10U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_MASK

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_MASK   (0x00000400U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_ENABLED

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLED

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLE

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION

#define ADC_IRQENABLE_CLR_HW_PEN_EVT_SYNCHRONOUS_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_SHIFT

#define ADC_IRQENABLE_CLR_FIFO1_THR_SHIFT   (5U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_MASK

#define ADC_IRQENABLE_CLR_FIFO1_THR_MASK   (0x00000020U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_ENABLED

#define ADC_IRQENABLE_CLR_FIFO1_THR_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_DISABLED

#define ADC_IRQENABLE_CLR_FIFO1_THR_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_DISABLE

#define ADC_IRQENABLE_CLR_FIFO1_THR_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_THR_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO1_THR_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_SHIFT

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_SHIFT   (4U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_MASK

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_MASK   (0x00000010U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_ENABLED

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLED

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLE

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_SHIFT

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_SHIFT   (9U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_MASK

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_MASK   (0x00000200U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_ENABLED

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLED

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLE

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_PEN_UP_EVT_NO_ACTION

#define ADC_IRQENABLE_CLR_PEN_UP_EVT_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_SHIFT

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_SHIFT   (1U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_MASK

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_MASK   (0x00000002U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_ENABLED

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLED

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLE

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_END_OF_SEQUENCE_NO_ACTION

#define ADC_IRQENABLE_CLR_END_OF_SEQUENCE_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SHIFT

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SHIFT   (0U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_MASK

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_MASK   (0x00000001U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_EVT_PEND

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_EVT_PEND   (1U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_EVT_PEND

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_EVT_PEND   (0U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SET_EVT

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_SET_EVT   (1U)

◆ ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_ACTION

#define ADC_IRQENABLE_CLR_AFE_EOC_MISSING_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_RESERVED0_SHIFT

#define ADC_IRQENABLE_CLR_RESERVED0_SHIFT   (11U)

◆ ADC_IRQENABLE_CLR_RESERVED0_MASK

#define ADC_IRQENABLE_CLR_RESERVED0_MASK   (0xfffff800U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_SHIFT

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_SHIFT   (7U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_MASK

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_MASK   (0x00000080U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_ENABLED

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLED

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLE

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_SHIFT

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_SHIFT   (8U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_MASK

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_MASK   (0x00000100U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_ENABLED

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLED

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLE

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_OUT_OF_RANGE_NO_ACTION

#define ADC_IRQENABLE_CLR_OUT_OF_RANGE_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_SHIFT

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_SHIFT   (6U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_MASK

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_MASK   (0x00000040U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_ENABLED

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLED

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLE

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO1_OVERRUN_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO1_OVERRUN_NO_ACTION   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_SHIFT

#define ADC_IRQENABLE_CLR_FIFO0_THR_SHIFT   (2U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_MASK

#define ADC_IRQENABLE_CLR_FIFO0_THR_MASK   (0x00000004U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_ENABLED

#define ADC_IRQENABLE_CLR_FIFO0_THR_ENABLED   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_DISABLED

#define ADC_IRQENABLE_CLR_FIFO0_THR_DISABLED   (0U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_DISABLE

#define ADC_IRQENABLE_CLR_FIFO0_THR_DISABLE   (1U)

◆ ADC_IRQENABLE_CLR_FIFO0_THR_NO_ACTION

#define ADC_IRQENABLE_CLR_FIFO0_THR_NO_ACTION   (0U)

◆ ADC_IRQWAKEUP_WAKEEN0_SHIFT

#define ADC_IRQWAKEUP_WAKEEN0_SHIFT   (0U)

◆ ADC_IRQWAKEUP_WAKEEN0_MASK

#define ADC_IRQWAKEUP_WAKEEN0_MASK   (0x00000001U)

◆ ADC_IRQWAKEUP_WAKEEN0_DISABLED

#define ADC_IRQWAKEUP_WAKEEN0_DISABLED   (0U)

◆ ADC_IRQWAKEUP_WAKEEN0_ENABLED

#define ADC_IRQWAKEUP_WAKEEN0_ENABLED   (1U)

◆ ADC_IRQWAKEUP_RESERVED0_SHIFT

#define ADC_IRQWAKEUP_RESERVED0_SHIFT   (1U)

◆ ADC_IRQWAKEUP_RESERVED0_MASK

#define ADC_IRQWAKEUP_RESERVED0_MASK   (0xfffffffeU)

◆ ADC_DMAENABLE_SET_EN_0_SHIFT

#define ADC_DMAENABLE_SET_EN_0_SHIFT   (0U)

◆ ADC_DMAENABLE_SET_EN_0_MASK

#define ADC_DMAENABLE_SET_EN_0_MASK   (0x00000001U)

◆ ADC_DMAENABLE_SET_EN_0_ENABLED

#define ADC_DMAENABLE_SET_EN_0_ENABLED   (1U)

◆ ADC_DMAENABLE_SET_EN_0_DISABLED

#define ADC_DMAENABLE_SET_EN_0_DISABLED   (0U)

◆ ADC_DMAENABLE_SET_EN_0_ENABLE

#define ADC_DMAENABLE_SET_EN_0_ENABLE   (1U)

◆ ADC_DMAENABLE_SET_EN_0_NO_ACTION

#define ADC_DMAENABLE_SET_EN_0_NO_ACTION   (0U)

◆ ADC_DMAENABLE_SET_RESERVED0_SHIFT

#define ADC_DMAENABLE_SET_RESERVED0_SHIFT   (2U)

◆ ADC_DMAENABLE_SET_RESERVED0_MASK

#define ADC_DMAENABLE_SET_RESERVED0_MASK   (0xfffffffcU)

◆ ADC_DMAENABLE_SET_EN_1_SHIFT

#define ADC_DMAENABLE_SET_EN_1_SHIFT   (1U)

◆ ADC_DMAENABLE_SET_EN_1_MASK

#define ADC_DMAENABLE_SET_EN_1_MASK   (0x00000002U)

◆ ADC_DMAENABLE_SET_EN_1_ENABLED

#define ADC_DMAENABLE_SET_EN_1_ENABLED   (1U)

◆ ADC_DMAENABLE_SET_EN_1_DISABLED

#define ADC_DMAENABLE_SET_EN_1_DISABLED   (0U)

◆ ADC_DMAENABLE_SET_EN_1_ENABLE

#define ADC_DMAENABLE_SET_EN_1_ENABLE   (1U)

◆ ADC_DMAENABLE_SET_EN_1_NO_ACTION

#define ADC_DMAENABLE_SET_EN_1_NO_ACTION   (0U)

◆ ADC_DMAENABLE_CLR_RESERVED0_SHIFT

#define ADC_DMAENABLE_CLR_RESERVED0_SHIFT   (2U)

◆ ADC_DMAENABLE_CLR_RESERVED0_MASK

#define ADC_DMAENABLE_CLR_RESERVED0_MASK   (0xfffffffcU)

◆ ADC_DMAENABLE_CLR_EN_1_SHIFT

#define ADC_DMAENABLE_CLR_EN_1_SHIFT   (1U)

◆ ADC_DMAENABLE_CLR_EN_1_MASK

#define ADC_DMAENABLE_CLR_EN_1_MASK   (0x00000002U)

◆ ADC_DMAENABLE_CLR_EN_1_ENABLED

#define ADC_DMAENABLE_CLR_EN_1_ENABLED   (1U)

◆ ADC_DMAENABLE_CLR_EN_1_DISABLED

#define ADC_DMAENABLE_CLR_EN_1_DISABLED   (0U)

◆ ADC_DMAENABLE_CLR_EN_1_DISABLE

#define ADC_DMAENABLE_CLR_EN_1_DISABLE   (1U)

◆ ADC_DMAENABLE_CLR_EN_1_NO_ACTION

#define ADC_DMAENABLE_CLR_EN_1_NO_ACTION   (0U)

◆ ADC_DMAENABLE_CLR_EN_0_SHIFT

#define ADC_DMAENABLE_CLR_EN_0_SHIFT   (0U)

◆ ADC_DMAENABLE_CLR_EN_0_MASK

#define ADC_DMAENABLE_CLR_EN_0_MASK   (0x00000001U)

◆ ADC_DMAENABLE_CLR_EN_0_ENABLED

#define ADC_DMAENABLE_CLR_EN_0_ENABLED   (1U)

◆ ADC_DMAENABLE_CLR_EN_0_DISABLED

#define ADC_DMAENABLE_CLR_EN_0_DISABLED   (0U)

◆ ADC_DMAENABLE_CLR_EN_0_DISABLE

#define ADC_DMAENABLE_CLR_EN_0_DISABLE   (1U)

◆ ADC_DMAENABLE_CLR_EN_0_NO_ACTION

#define ADC_DMAENABLE_CLR_EN_0_NO_ACTION   (0U)

◆ ADC_CTRL_STEP_ID_TAG_SHIFT

#define ADC_CTRL_STEP_ID_TAG_SHIFT   (1U)

◆ ADC_CTRL_STEP_ID_TAG_MASK

#define ADC_CTRL_STEP_ID_TAG_MASK   (0x00000002U)

◆ ADC_CTRL_STEP_ID_TAG_WRZERO

#define ADC_CTRL_STEP_ID_TAG_WRZERO   (0U)

◆ ADC_CTRL_STEP_ID_TAG_CHANNELID

#define ADC_CTRL_STEP_ID_TAG_CHANNELID   (1U)

◆ ADC_CTRL_EN_SHIFT

#define ADC_CTRL_EN_SHIFT   (0U)

◆ ADC_CTRL_EN_MASK

#define ADC_CTRL_EN_MASK   (0x00000001U)

◆ ADC_CTRL_EN_DISABLE

#define ADC_CTRL_EN_DISABLE   (0U)

◆ ADC_CTRL_EN_ENABLE

#define ADC_CTRL_EN_ENABLE   (1U)

◆ ADC_CTRL_POWER_DOWN_SHIFT

#define ADC_CTRL_POWER_DOWN_SHIFT   (4U)

◆ ADC_CTRL_POWER_DOWN_MASK

#define ADC_CTRL_POWER_DOWN_MASK   (0x00000010U)

◆ ADC_CTRL_POWER_DOWN_AFEPOWERUP

#define ADC_CTRL_POWER_DOWN_AFEPOWERUP   (0U)

◆ ADC_CTRL_POWER_DOWN_AFEPOWERDOWN

#define ADC_CTRL_POWER_DOWN_AFEPOWERDOWN   (1U)

◆ ADC_CTRL_HW_PREEMPT_SHIFT

#define ADC_CTRL_HW_PREEMPT_SHIFT   (9U)

◆ ADC_CTRL_HW_PREEMPT_MASK

#define ADC_CTRL_HW_PREEMPT_MASK   (0x00000200U)

◆ ADC_CTRL_HW_PREEMPT_NOPREEMPT

#define ADC_CTRL_HW_PREEMPT_NOPREEMPT   (0U)

◆ ADC_CTRL_HW_PREEMPT

#define ADC_CTRL_HW_PREEMPT   (1U)

◆ ADC_CTRL_AFE_PEN_SHIFT

#define ADC_CTRL_AFE_PEN_SHIFT   (5U)

◆ ADC_CTRL_AFE_PEN_MASK

#define ADC_CTRL_AFE_PEN_MASK   (0x00000060U)

◆ ADC_CTRL_RESERVED0_SHIFT

#define ADC_CTRL_RESERVED0_SHIFT   (10U)

◆ ADC_CTRL_RESERVED0_MASK

#define ADC_CTRL_RESERVED0_MASK   (0xfffffc00U)

◆ ADC_CTRL_TOUCH_SCREEN_EN_SHIFT

#define ADC_CTRL_TOUCH_SCREEN_EN_SHIFT   (7U)

◆ ADC_CTRL_TOUCH_SCREEN_EN_MASK

#define ADC_CTRL_TOUCH_SCREEN_EN_MASK   (0x00000080U)

◆ ADC_CTRL_TOUCH_SCREEN_EN_DISABLE

#define ADC_CTRL_TOUCH_SCREEN_EN_DISABLE   (0U)

◆ ADC_CTRL_TOUCH_SCREEN_EN_ENABLE

#define ADC_CTRL_TOUCH_SCREEN_EN_ENABLE   (1U)

◆ ADC_CTRL_HW_EVT_MAPPING_SHIFT

#define ADC_CTRL_HW_EVT_MAPPING_SHIFT   (8U)

◆ ADC_CTRL_HW_EVT_MAPPING_MASK

#define ADC_CTRL_HW_EVT_MAPPING_MASK   (0x00000100U)

◆ ADC_CTRL_HW_EVT_MAPPING_PENTOUCHIRQ

#define ADC_CTRL_HW_EVT_MAPPING_PENTOUCHIRQ   (0U)

◆ ADC_CTRL_HW_EVT_MAPPING_HWEVTINPUT

#define ADC_CTRL_HW_EVT_MAPPING_HWEVTINPUT   (1U)

◆ ADC_CTRL_BIAS_SELECT_SHIFT

#define ADC_CTRL_BIAS_SELECT_SHIFT   (3U)

◆ ADC_CTRL_BIAS_SELECT_MASK

#define ADC_CTRL_BIAS_SELECT_MASK   (0x00000008U)

◆ ADC_CTRL_BIAS_SELECT_INTERNAL

#define ADC_CTRL_BIAS_SELECT_INTERNAL   (0U)

◆ ADC_CTRL_BIAS_SELECT_EXTERNAL

#define ADC_CTRL_BIAS_SELECT_EXTERNAL   (1U)

◆ ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_SHIFT

#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_SHIFT   (2U)

◆ ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_MASK

#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_MASK   (0x00000004U)

◆ ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_PROTECTED

#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_PROTECTED   (0U)

◆ ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_NOTPROTECTED

#define ADC_CTRL_STEPCONFIG_WRITEPROTECT_N_NOTPROTECTED   (1U)

◆ ADC_CTRL_HW_MID_EN_SHIFT

#define ADC_CTRL_HW_MID_EN_SHIFT   (10U)

◆ ADC_CTRL_HW_MID_EN_MASK

#define ADC_CTRL_HW_MID_EN_MASK   (0x00000400U)

◆ ADC_CTRL_HW_MID_EN_DISABLE

#define ADC_CTRL_HW_MID_EN_DISABLE   (0U)

◆ ADC_CTRL_HW_MID_EN_ENABLE

#define ADC_CTRL_HW_MID_EN_ENABLE   (1U)

◆ ADC_CTRL_HW_MID_SEL_SHIFT

#define ADC_CTRL_HW_MID_SEL_SHIFT   (11U)

◆ ADC_CTRL_HW_MID_SEL_MASK

#define ADC_CTRL_HW_MID_SEL_MASK   (0x00000800U)

◆ ADC_CTRL_HW_MID_SEL_DISABLE

#define ADC_CTRL_HW_MID_SEL_DISABLE   (0U)

◆ ADC_CTRL_HW_MID_SEL_ENABLE

#define ADC_CTRL_HW_MID_SEL_ENABLE   (1U)

◆ ADC_ADCSTAT_MEM_INIT_DONE_SHIFT

#define ADC_ADCSTAT_MEM_INIT_DONE_SHIFT   (6U)

◆ ADC_ADCSTAT_MEM_INIT_DONE_MASK

#define ADC_ADCSTAT_MEM_INIT_DONE_MASK   (0x00000040U)

◆ ADC_ADCSTAT_MEM_INIT_DONE_RESETVAL

#define ADC_ADCSTAT_MEM_INIT_DONE_RESETVAL   (0U)

◆ ADC_ADCSTAT_MEM_INIT_DONE

#define ADC_ADCSTAT_MEM_INIT_DONE   (1U)

◆ ADC_ADCSTAT_RESERVED0_SHIFT

#define ADC_ADCSTAT_RESERVED0_SHIFT   (9U)

◆ ADC_ADCSTAT_RESERVED0_MASK

#define ADC_ADCSTAT_RESERVED0_MASK   (0xfffffe00U)

◆ ADC_ADCSTAT_AFE_BUSY_SHIFT

#define ADC_ADCSTAT_AFE_BUSY_SHIFT   (8U)

◆ ADC_ADCSTAT_AFE_BUSY_MASK

#define ADC_ADCSTAT_AFE_BUSY_MASK   (0x00000100U)

◆ ADC_ADCSTAT_AFE_BUSY_IDLE

#define ADC_ADCSTAT_AFE_BUSY_IDLE   (0U)

◆ ADC_ADCSTAT_AFE_BUSY

#define ADC_ADCSTAT_AFE_BUSY   (1U)

◆ ADC_ADCSTAT_FSM_BUSY_SHIFT

#define ADC_ADCSTAT_FSM_BUSY_SHIFT   (5U)

◆ ADC_ADCSTAT_FSM_BUSY_MASK

#define ADC_ADCSTAT_FSM_BUSY_MASK   (0x00000020U)

◆ ADC_ADCSTAT_FSM_BUSY_IDLE

#define ADC_ADCSTAT_FSM_BUSY_IDLE   (0U)

◆ ADC_ADCSTAT_FSM_BUSY

#define ADC_ADCSTAT_FSM_BUSY   (1U)

◆ ADC_ADCSTAT_STEP_ID_SHIFT

#define ADC_ADCSTAT_STEP_ID_SHIFT   (0U)

◆ ADC_ADCSTAT_STEP_ID_MASK

#define ADC_ADCSTAT_STEP_ID_MASK   (0x0000001fU)

◆ ADC_ADCSTAT_STEP_ID_STEP1

#define ADC_ADCSTAT_STEP_ID_STEP1   (0U)

◆ ADC_ADCSTAT_STEP_ID_STEP2

#define ADC_ADCSTAT_STEP_ID_STEP2   (1U)

◆ ADC_ADCSTAT_STEP_ID_STEP3

#define ADC_ADCSTAT_STEP_ID_STEP3   (2U)

◆ ADC_ADCSTAT_STEP_ID_STEP4

#define ADC_ADCSTAT_STEP_ID_STEP4   (3U)

◆ ADC_ADCSTAT_STEP_ID_STEP5

#define ADC_ADCSTAT_STEP_ID_STEP5   (4U)

◆ ADC_ADCSTAT_STEP_ID_STEP6

#define ADC_ADCSTAT_STEP_ID_STEP6   (5U)

◆ ADC_ADCSTAT_STEP_ID_STEP7

#define ADC_ADCSTAT_STEP_ID_STEP7   (6U)

◆ ADC_ADCSTAT_STEP_ID_STEP8

#define ADC_ADCSTAT_STEP_ID_STEP8   (7U)

◆ ADC_ADCSTAT_STEP_ID_STEP9

#define ADC_ADCSTAT_STEP_ID_STEP9   (8U)

◆ ADC_ADCSTAT_STEP_ID_STEP10

#define ADC_ADCSTAT_STEP_ID_STEP10   (9U)

◆ ADC_ADCSTAT_STEP_ID_STEP11

#define ADC_ADCSTAT_STEP_ID_STEP11   (10U)

◆ ADC_ADCSTAT_STEP_ID_STEP12

#define ADC_ADCSTAT_STEP_ID_STEP12   (11U)

◆ ADC_ADCSTAT_STEP_ID_STEP13

#define ADC_ADCSTAT_STEP_ID_STEP13   (12U)

◆ ADC_ADCSTAT_STEP_ID_STEP14

#define ADC_ADCSTAT_STEP_ID_STEP14   (13U)

◆ ADC_ADCSTAT_STEP_ID_STEP15

#define ADC_ADCSTAT_STEP_ID_STEP15   (14U)

◆ ADC_ADCSTAT_STEP_ID_STEP16

#define ADC_ADCSTAT_STEP_ID_STEP16   (15U)

◆ ADC_ADCSTAT_STEP_ID_IDLE

#define ADC_ADCSTAT_STEP_ID_IDLE   (16U)

◆ ADC_ADCSTAT_STEP_ID_CHARGE

#define ADC_ADCSTAT_STEP_ID_CHARGE   (17U)

◆ ADC_ADCSTAT_PEN_IRQ1_SHIFT

#define ADC_ADCSTAT_PEN_IRQ1_SHIFT   (7U)

◆ ADC_ADCSTAT_PEN_IRQ1_MASK

#define ADC_ADCSTAT_PEN_IRQ1_MASK   (0x00000080U)

◆ ADC_ADCRANGE_RESERVED1_SHIFT

#define ADC_ADCRANGE_RESERVED1_SHIFT   (28U)

◆ ADC_ADCRANGE_RESERVED1_MASK

#define ADC_ADCRANGE_RESERVED1_MASK   (0xf0000000U)

◆ ADC_ADCRANGE_HIGH_RANGE_DATA_SHIFT

#define ADC_ADCRANGE_HIGH_RANGE_DATA_SHIFT   (16U)

◆ ADC_ADCRANGE_HIGH_RANGE_DATA_MASK

#define ADC_ADCRANGE_HIGH_RANGE_DATA_MASK   (0x0fff0000U)

◆ ADC_ADCRANGE_LOW_RANGE_DATA_SHIFT

#define ADC_ADCRANGE_LOW_RANGE_DATA_SHIFT   (0U)

◆ ADC_ADCRANGE_LOW_RANGE_DATA_MASK

#define ADC_ADCRANGE_LOW_RANGE_DATA_MASK   (0x00000fffU)

◆ ADC_ADCRANGE_RESERVED0_SHIFT

#define ADC_ADCRANGE_RESERVED0_SHIFT   (12U)

◆ ADC_ADCRANGE_RESERVED0_MASK

#define ADC_ADCRANGE_RESERVED0_MASK   (0x0000f000U)

◆ ADC_MISC_AFE_SPARE_INPUT_SHIFT

#define ADC_MISC_AFE_SPARE_INPUT_SHIFT   (0U)

◆ ADC_MISC_AFE_SPARE_INPUT_MASK

#define ADC_MISC_AFE_SPARE_INPUT_MASK   (0x0000000fU)

◆ ADC_MISC_RESERVED0_SHIFT

#define ADC_MISC_RESERVED0_SHIFT   (8U)

◆ ADC_MISC_RESERVED0_MASK

#define ADC_MISC_RESERVED0_MASK   (0xffffff00U)

◆ ADC_MISC_AFE_SPARE_OUTPUT_SHIFT

#define ADC_MISC_AFE_SPARE_OUTPUT_SHIFT   (8U)

◆ ADC_MISC_AFE_SPARE_OUTPUT_MASK

#define ADC_MISC_AFE_SPARE_OUTPUT_MASK   (0x00000f00U)

◆ ADC_STEPENABLE_STEP_SHIFT

#define ADC_STEPENABLE_STEP_SHIFT   (1U)

◆ ADC_STEPENABLE_STEP_MASK

#define ADC_STEPENABLE_STEP_MASK   (0x0001FFFEU)

◆ ADC_STEPENABLE_STEP3_SHIFT

#define ADC_STEPENABLE_STEP3_SHIFT   (3U)

◆ ADC_STEPENABLE_STEP3_MASK

#define ADC_STEPENABLE_STEP3_MASK   (0x00000008U)

◆ ADC_STEPENABLE_STEP8_SHIFT

#define ADC_STEPENABLE_STEP8_SHIFT   (8U)

◆ ADC_STEPENABLE_STEP8_MASK

#define ADC_STEPENABLE_STEP8_MASK   (0x00000100U)

◆ ADC_STEPENABLE_STEP2_SHIFT

#define ADC_STEPENABLE_STEP2_SHIFT   (2U)

◆ ADC_STEPENABLE_STEP2_MASK

#define ADC_STEPENABLE_STEP2_MASK   (0x00000004U)

◆ ADC_STEPENABLE_STEP16_SHIFT

#define ADC_STEPENABLE_STEP16_SHIFT   (16U)

◆ ADC_STEPENABLE_STEP16_MASK

#define ADC_STEPENABLE_STEP16_MASK   (0x00010000U)

◆ ADC_STEPENABLE_STEP15_SHIFT

#define ADC_STEPENABLE_STEP15_SHIFT   (15U)

◆ ADC_STEPENABLE_STEP15_MASK

#define ADC_STEPENABLE_STEP15_MASK   (0x00008000U)

◆ ADC_STEPENABLE_STEP12_SHIFT

#define ADC_STEPENABLE_STEP12_SHIFT   (12U)

◆ ADC_STEPENABLE_STEP12_MASK

#define ADC_STEPENABLE_STEP12_MASK   (0x00001000U)

◆ ADC_STEPENABLE_STEP13_SHIFT

#define ADC_STEPENABLE_STEP13_SHIFT   (13U)

◆ ADC_STEPENABLE_STEP13_MASK

#define ADC_STEPENABLE_STEP13_MASK   (0x00002000U)

◆ ADC_STEPENABLE_RESERVED0_SHIFT

#define ADC_STEPENABLE_RESERVED0_SHIFT   (17U)

◆ ADC_STEPENABLE_RESERVED0_MASK

#define ADC_STEPENABLE_RESERVED0_MASK   (0xfffe0000U)

◆ ADC_STEPENABLE_STEP14_SHIFT

#define ADC_STEPENABLE_STEP14_SHIFT   (14U)

◆ ADC_STEPENABLE_STEP14_MASK

#define ADC_STEPENABLE_STEP14_MASK   (0x00004000U)

◆ ADC_STEPENABLE_STEP7_SHIFT

#define ADC_STEPENABLE_STEP7_SHIFT   (7U)

◆ ADC_STEPENABLE_STEP7_MASK

#define ADC_STEPENABLE_STEP7_MASK   (0x00000080U)

◆ ADC_STEPENABLE_STEP9_SHIFT

#define ADC_STEPENABLE_STEP9_SHIFT   (9U)

◆ ADC_STEPENABLE_STEP9_MASK

#define ADC_STEPENABLE_STEP9_MASK   (0x00000200U)

◆ ADC_STEPENABLE_STEP10_SHIFT

#define ADC_STEPENABLE_STEP10_SHIFT   (10U)

◆ ADC_STEPENABLE_STEP10_MASK

#define ADC_STEPENABLE_STEP10_MASK   (0x00000400U)

◆ ADC_STEPENABLE_STEP4_SHIFT

#define ADC_STEPENABLE_STEP4_SHIFT   (4U)

◆ ADC_STEPENABLE_STEP4_MASK

#define ADC_STEPENABLE_STEP4_MASK   (0x00000010U)

◆ ADC_STEPENABLE_STEP1_SHIFT

#define ADC_STEPENABLE_STEP1_SHIFT   (1U)

◆ ADC_STEPENABLE_STEP1_MASK

#define ADC_STEPENABLE_STEP1_MASK   (0x00000002U)

◆ ADC_STEPENABLE_STEP5_SHIFT

#define ADC_STEPENABLE_STEP5_SHIFT   (5U)

◆ ADC_STEPENABLE_STEP5_MASK

#define ADC_STEPENABLE_STEP5_MASK   (0x00000020U)

◆ ADC_STEPENABLE_STEP11_SHIFT

#define ADC_STEPENABLE_STEP11_SHIFT   (11U)

◆ ADC_STEPENABLE_STEP11_MASK

#define ADC_STEPENABLE_STEP11_MASK   (0x00000800U)

◆ ADC_STEPENABLE_STEP6_SHIFT

#define ADC_STEPENABLE_STEP6_SHIFT   (6U)

◆ ADC_STEPENABLE_STEP6_MASK

#define ADC_STEPENABLE_STEP6_MASK   (0x00000040U)

◆ ADC_STEPENABLE_TS_CHARGE_SHIFT

#define ADC_STEPENABLE_TS_CHARGE_SHIFT   (0U)

◆ ADC_STEPENABLE_TS_CHARGE_MASK

#define ADC_STEPENABLE_TS_CHARGE_MASK   (0x00000001U)

◆ ADC_IDLECONFIG_XPPSW_SWC_SHIFT

#define ADC_IDLECONFIG_XPPSW_SWC_SHIFT   (5U)

◆ ADC_IDLECONFIG_XPPSW_SWC_MASK

#define ADC_IDLECONFIG_XPPSW_SWC_MASK   (0x00000020U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_SHIFT

#define ADC_IDLECONFIG_SEL_RFP_SWC_SHIFT   (12U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_MASK

#define ADC_IDLECONFIG_SEL_RFP_SWC_MASK   (0x00007000U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_VDDA

#define ADC_IDLECONFIG_SEL_RFP_SWC_VDDA   (0U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_XPUL

#define ADC_IDLECONFIG_SEL_RFP_SWC_XPUL   (1U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_YPLL

#define ADC_IDLECONFIG_SEL_RFP_SWC_YPLL   (2U)

◆ ADC_IDLECONFIG_SEL_RFP_SWC_VREFP

#define ADC_IDLECONFIG_SEL_RFP_SWC_VREFP   (3U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_SHIFT

#define ADC_IDLECONFIG_SEL_INM_SWM_SHIFT   (15U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_MASK

#define ADC_IDLECONFIG_SEL_INM_SWM_MASK   (0x00078000U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_1

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_1   (0U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_2

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_2   (1U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_3

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_3   (2U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_4

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_4   (3U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_5

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_5   (4U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_6

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_6   (5U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_7

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_7   (6U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_8

#define ADC_IDLECONFIG_SEL_INM_SWM_CHANNEL_8   (7U)

◆ ADC_IDLECONFIG_SEL_INM_SWM_VREFN

#define ADC_IDLECONFIG_SEL_INM_SWM_VREFN   (8U)

◆ ADC_IDLECONFIG_RESERVED0_SHIFT

#define ADC_IDLECONFIG_RESERVED0_SHIFT   (0U)

◆ ADC_IDLECONFIG_RESERVED0_MASK

#define ADC_IDLECONFIG_RESERVED0_MASK   (0x0000001fU)

◆ ADC_IDLECONFIG_YPPSW_SWC_SHIFT

#define ADC_IDLECONFIG_YPPSW_SWC_SHIFT   (7U)

◆ ADC_IDLECONFIG_YPPSW_SWC_MASK

#define ADC_IDLECONFIG_YPPSW_SWC_MASK   (0x00000080U)

◆ ADC_IDLECONFIG_YPNSW_SWC_SHIFT

#define ADC_IDLECONFIG_YPNSW_SWC_SHIFT   (10U)

◆ ADC_IDLECONFIG_YPNSW_SWC_MASK

#define ADC_IDLECONFIG_YPNSW_SWC_MASK   (0x00000400U)

◆ ADC_IDLECONFIG_RESERVED1_SHIFT

#define ADC_IDLECONFIG_RESERVED1_SHIFT   (26U)

◆ ADC_IDLECONFIG_RESERVED1_MASK

#define ADC_IDLECONFIG_RESERVED1_MASK   (0xfc000000U)

◆ ADC_IDLECONFIG_XNNSW_SWC_SHIFT

#define ADC_IDLECONFIG_XNNSW_SWC_SHIFT   (6U)

◆ ADC_IDLECONFIG_XNNSW_SWC_MASK

#define ADC_IDLECONFIG_XNNSW_SWC_MASK   (0x00000040U)

◆ ADC_IDLECONFIG_XNPSW_SWC_SHIFT

#define ADC_IDLECONFIG_XNPSW_SWC_SHIFT   (9U)

◆ ADC_IDLECONFIG_XNPSW_SWC_MASK

#define ADC_IDLECONFIG_XNPSW_SWC_MASK   (0x00000200U)

◆ ADC_IDLECONFIG_YNNSW_SWC_SHIFT

#define ADC_IDLECONFIG_YNNSW_SWC_SHIFT   (8U)

◆ ADC_IDLECONFIG_YNNSW_SWC_MASK

#define ADC_IDLECONFIG_YNNSW_SWC_MASK   (0x00000100U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_SHIFT

#define ADC_IDLECONFIG_SEL_RFM_SWC_SHIFT   (23U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_MASK

#define ADC_IDLECONFIG_SEL_RFM_SWC_MASK   (0x01800000U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_VSSA

#define ADC_IDLECONFIG_SEL_RFM_SWC_VSSA   (0U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_XNUR

#define ADC_IDLECONFIG_SEL_RFM_SWC_XNUR   (1U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_YNLR

#define ADC_IDLECONFIG_SEL_RFM_SWC_YNLR   (2U)

◆ ADC_IDLECONFIG_SEL_RFM_SWC_VREFN

#define ADC_IDLECONFIG_SEL_RFM_SWC_VREFN   (3U)

◆ ADC_IDLECONFIG_WPNSW_SWC_SHIFT

#define ADC_IDLECONFIG_WPNSW_SWC_SHIFT   (11U)

◆ ADC_IDLECONFIG_WPNSW_SWC_MASK

#define ADC_IDLECONFIG_WPNSW_SWC_MASK   (0x00000800U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_SHIFT

#define ADC_IDLECONFIG_SEL_INP_SWC_SHIFT   (19U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_MASK

#define ADC_IDLECONFIG_SEL_INP_SWC_MASK   (0x00780000U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_1

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_1   (0U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_2

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_2   (1U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_3

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_3   (2U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_4

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_4   (3U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_5

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_5   (4U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_6

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_6   (5U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_7

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_7   (6U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_8

#define ADC_IDLECONFIG_SEL_INP_SWC_CHANNEL_8   (7U)

◆ ADC_IDLECONFIG_SEL_INP_SWC_VREFN

#define ADC_IDLECONFIG_SEL_INP_SWC_VREFN   (8U)

◆ ADC_IDLECONFIG_DIFF_CNTRL_SHIFT

#define ADC_IDLECONFIG_DIFF_CNTRL_SHIFT   (25U)

◆ ADC_IDLECONFIG_DIFF_CNTRL_MASK

#define ADC_IDLECONFIG_DIFF_CNTRL_MASK   (0x02000000U)

◆ ADC_IDLECONFIG_DIFF_CNTRL_SINGLE

#define ADC_IDLECONFIG_DIFF_CNTRL_SINGLE   (0U)

◆ ADC_IDLECONFIG_DIFF_CNTRL_DIFFERENTIAL

#define ADC_IDLECONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SHIFT   (25U)

◆ ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_MASK

#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_MASK   (0x02000000U)

◆ ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SINGLE

#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SINGLE   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL

#define ADC_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_SHIFT   (9U)

◆ ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_XNPSW_SWC_MASK   (0x00000200U)

◆ ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_SHIFT   (10U)

◆ ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_YPNSW_SWC_MASK   (0x00000400U)

◆ ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_SHIFT   (5U)

◆ ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_XPPSW_SWC_MASK   (0x00000020U)

◆ ADC_TS_CHARGE_STEPCONFIG_RESERVED0_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_RESERVED0_SHIFT   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_RESERVED0_MASK

#define ADC_TS_CHARGE_STEPCONFIG_RESERVED0_MASK   (0x0000001fU)

◆ ADC_TS_CHARGE_STEPCONFIG_RESERVED1_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_RESERVED1_SHIFT   (26U)

◆ ADC_TS_CHARGE_STEPCONFIG_RESERVED1_MASK

#define ADC_TS_CHARGE_STEPCONFIG_RESERVED1_MASK   (0xfc000000U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_SHIFT   (15U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_MASK

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_MASK   (0x00078000U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_1

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_1   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_2

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_2   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_3

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_3   (2U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_4

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_4   (3U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_5

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_5   (4U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_6

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_6   (5U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_7

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_7   (6U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_8

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_CHANNEL_8   (7U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_VREFN

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_VREFN   (8U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_SHIFT   (12U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_MASK   (0x00007000U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VDDA

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VDDA   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_XPUL

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_XPUL   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_YPLL

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_YPLL   (2U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VREFP

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_VREFP   (3U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_INTREF

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_INTREF   (4U)

◆ ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_SHIFT   (11U)

◆ ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_WPNSW_SWC_MASK   (0x00000800U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_SHIFT   (19U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_MASK   (0x00780000U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_1

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_1   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_2

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_2   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_3

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_3   (2U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_4

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_4   (3U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_5

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_5   (4U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_6

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_6   (5U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_7

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_7   (6U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_8

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_CHANNEL_8   (7U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_VREFN

#define ADC_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_VREFN   (8U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_SHIFT   (23U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_MASK   (0x01800000U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VSSA

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VSSA   (0U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_XNUR

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_XNUR   (1U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_YNLR

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_YNLR   (2U)

◆ ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VREFN

#define ADC_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_VREFN   (3U)

◆ ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_SHIFT   (7U)

◆ ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_YPPSW__SWC_MASK   (0x00000080U)

◆ ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_SHIFT   (6U)

◆ ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_XNNSW__SWC_MASK   (0x00000040U)

◆ ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_SHIFT

#define ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_SHIFT   (8U)

◆ ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_MASK

#define ADC_TS_CHARGE_STEPCONFIG_YNNSW_SWC_MASK   (0x00000100U)

◆ ADC_TS_CHARGE_DELAY_OPENDELAY_SHIFT

#define ADC_TS_CHARGE_DELAY_OPENDELAY_SHIFT   (0U)

◆ ADC_TS_CHARGE_DELAY_OPENDELAY_MASK

#define ADC_TS_CHARGE_DELAY_OPENDELAY_MASK   (0x0003ffffU)

◆ ADC_TS_CHARGE_DELAY_RESERVED0_SHIFT

#define ADC_TS_CHARGE_DELAY_RESERVED0_SHIFT   (18U)

◆ ADC_TS_CHARGE_DELAY_RESERVED0_MASK

#define ADC_TS_CHARGE_DELAY_RESERVED0_MASK   (0xfffc0000U)

◆ ADC_IRQ_EOI_LINE_NUMBER_SHIFT

#define ADC_IRQ_EOI_LINE_NUMBER_SHIFT   (0U)

◆ ADC_IRQ_EOI_LINE_NUMBER_MASK

#define ADC_IRQ_EOI_LINE_NUMBER_MASK   (0x00000001U)

◆ ADC_IRQ_EOI_LINE_NUMBER_EOI

#define ADC_IRQ_EOI_LINE_NUMBER_EOI   (0U)

◆ ADC_IRQ_EOI_RESERVED0_SHIFT

#define ADC_IRQ_EOI_RESERVED0_SHIFT   (1U)

◆ ADC_IRQ_EOI_RESERVED0_MASK

#define ADC_IRQ_EOI_RESERVED0_MASK   (0x7ffffffeU)

◆ ADC_STEPCONFIG_YNNSW_SWC_SHIFT

#define ADC_STEPCONFIG_YNNSW_SWC_SHIFT   (8U)

◆ ADC_STEPCONFIG_YNNSW_SWC_MASK

#define ADC_STEPCONFIG_YNNSW_SWC_MASK   (0x00000100U)

◆ ADC_STEPCONFIG_DIFF_CNTRL_SHIFT

#define ADC_STEPCONFIG_DIFF_CNTRL_SHIFT   (25U)

◆ ADC_STEPCONFIG_DIFF_CNTRL_MASK

#define ADC_STEPCONFIG_DIFF_CNTRL_MASK   (0x02000000U)

◆ ADC_STEPCONFIG_DIFF_CNTRL_SINGLE

#define ADC_STEPCONFIG_DIFF_CNTRL_SINGLE   (0U)

◆ ADC_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL

#define ADC_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL   (1U)

◆ ADC_STEPCONFIG_WPNSW_SWC_SHIFT

#define ADC_STEPCONFIG_WPNSW_SWC_SHIFT   (11U)

◆ ADC_STEPCONFIG_WPNSW_SWC_MASK

#define ADC_STEPCONFIG_WPNSW_SWC_MASK   (0x00000800U)

◆ ADC_STEPCONFIG_MODE_SHIFT

#define ADC_STEPCONFIG_MODE_SHIFT   (0U)

◆ ADC_STEPCONFIG_MODE_MASK

#define ADC_STEPCONFIG_MODE_MASK   (0x00000003U)

◆ ADC_STEPCONFIG_MODE_SW_EN_ONESHOT

#define ADC_STEPCONFIG_MODE_SW_EN_ONESHOT   (0U)

◆ ADC_STEPCONFIG_MODE_SW_EN_CONTINUOUS

#define ADC_STEPCONFIG_MODE_SW_EN_CONTINUOUS   (1U)

◆ ADC_STEPCONFIG_MODE_HW_SYNC_ONESHOT

#define ADC_STEPCONFIG_MODE_HW_SYNC_ONESHOT   (2U)

◆ ADC_STEPCONFIG_MODE_HW_SYNC_CONTINUOUS

#define ADC_STEPCONFIG_MODE_HW_SYNC_CONTINUOUS   (3U)

◆ ADC_STEPCONFIG_AVERAGING_SHIFT

#define ADC_STEPCONFIG_AVERAGING_SHIFT   (2U)

◆ ADC_STEPCONFIG_AVERAGING_MASK

#define ADC_STEPCONFIG_AVERAGING_MASK   (0x0000001cU)

◆ ADC_STEPCONFIG_AVERAGING_NOAVG

#define ADC_STEPCONFIG_AVERAGING_NOAVG   (0U)

◆ ADC_STEPCONFIG_AVERAGING_2_SAMPLESAVG

#define ADC_STEPCONFIG_AVERAGING_2_SAMPLESAVG   (1U)

◆ ADC_STEPCONFIG_AVERAGING_4_SAMPLESAVG

#define ADC_STEPCONFIG_AVERAGING_4_SAMPLESAVG   (2U)

◆ ADC_STEPCONFIG_AVERAGING_8_SAMPLESAVG

#define ADC_STEPCONFIG_AVERAGING_8_SAMPLESAVG   (3U)

◆ ADC_STEPCONFIG_AVERAGING_16_SAMPLESAV

#define ADC_STEPCONFIG_AVERAGING_16_SAMPLESAV   (4U)

◆ ADC_STEPCONFIG_XPPSW_SWC_SHIFT

#define ADC_STEPCONFIG_XPPSW_SWC_SHIFT   (5U)

◆ ADC_STEPCONFIG_XPPSW_SWC_MASK

#define ADC_STEPCONFIG_XPPSW_SWC_MASK   (0x00000020U)

◆ ADC_STEPCONFIG_YPPSW_SWC_SHIFT

#define ADC_STEPCONFIG_YPPSW_SWC_SHIFT   (7U)

◆ ADC_STEPCONFIG_YPPSW_SWC_MASK

#define ADC_STEPCONFIG_YPPSW_SWC_MASK   (0x00000080U)

◆ ADC_STEPCONFIG_XNNSW_SWC_SHIFT

#define ADC_STEPCONFIG_XNNSW_SWC_SHIFT   (6U)

◆ ADC_STEPCONFIG_XNNSW_SWC_MASK

#define ADC_STEPCONFIG_XNNSW_SWC_MASK   (0x00000040U)

◆ ADC_STEPCONFIG_FIFO_SELECT_SHIFT

#define ADC_STEPCONFIG_FIFO_SELECT_SHIFT   (26U)

◆ ADC_STEPCONFIG_FIFO_SELECT_MASK

#define ADC_STEPCONFIG_FIFO_SELECT_MASK   (0x04000000U)

◆ ADC_STEPCONFIG_FIFO_SELECT_0

#define ADC_STEPCONFIG_FIFO_SELECT_0   (0U)

◆ ADC_STEPCONFIG_FIFO_SELECT_1

#define ADC_STEPCONFIG_FIFO_SELECT_1   (1U)

◆ ADC_STEPCONFIG_RESERVED0_SHIFT

#define ADC_STEPCONFIG_RESERVED0_SHIFT   (28U)

◆ ADC_STEPCONFIG_RESERVED0_MASK

#define ADC_STEPCONFIG_RESERVED0_MASK   (0xf0000000U)

◆ ADC_STEPCONFIG_RANGE_CHECK_SHIFT

#define ADC_STEPCONFIG_RANGE_CHECK_SHIFT   (27U)

◆ ADC_STEPCONFIG_RANGE_CHECK_MASK

#define ADC_STEPCONFIG_RANGE_CHECK_MASK   (0x08000000U)

◆ ADC_STEPCONFIG_RANGE_CHECK_DISABLE

#define ADC_STEPCONFIG_RANGE_CHECK_DISABLE   (0U)

◆ ADC_STEPCONFIG_RANGE_CHECK_ENABLE

#define ADC_STEPCONFIG_RANGE_CHECK_ENABLE   (1U)

◆ ADC_STEPCONFIG_YPNSW_SWC_SHIFT

#define ADC_STEPCONFIG_YPNSW_SWC_SHIFT   (10U)

◆ ADC_STEPCONFIG_YPNSW_SWC_MASK

#define ADC_STEPCONFIG_YPNSW_SWC_MASK   (0x00000400U)

◆ ADC_STEPCONFIG_XNPSW_SWC_SHIFT

#define ADC_STEPCONFIG_XNPSW_SWC_SHIFT   (9U)

◆ ADC_STEPCONFIG_XNPSW_SWC_MASK

#define ADC_STEPCONFIG_XNPSW_SWC_MASK   (0x00000200U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_SHIFT

#define ADC_STEPCONFIG_SEL_RFP_SWC_SHIFT   (12U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_MASK

#define ADC_STEPCONFIG_SEL_RFP_SWC_MASK   (0x00007000U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_VDDA

#define ADC_STEPCONFIG_SEL_RFP_SWC_VDDA   (0U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_XPUL

#define ADC_STEPCONFIG_SEL_RFP_SWC_XPUL   (1U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_YPLL

#define ADC_STEPCONFIG_SEL_RFP_SWC_YPLL   (2U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_VREFP

#define ADC_STEPCONFIG_SEL_RFP_SWC_VREFP   (3U)

◆ ADC_STEPCONFIG_SEL_RFP_SWC_INTREF

#define ADC_STEPCONFIG_SEL_RFP_SWC_INTREF   (4U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_SHIFT

#define ADC_STEPCONFIG_SEL_INM_SWC_SHIFT   (15U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_MASK

#define ADC_STEPCONFIG_SEL_INM_SWC_MASK   (0x00078000U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_1

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_1   (0U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_2

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_2   (1U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_3

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_3   (2U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_4

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_4   (3U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_5

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_5   (4U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_6

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_6   (5U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_7

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_7   (6U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_8

#define ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_8   (7U)

◆ ADC_STEPCONFIG_SEL_INM_SWC_VREFN

#define ADC_STEPCONFIG_SEL_INM_SWC_VREFN   (8U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_SHIFT

#define ADC_STEPCONFIG_SEL_INP_SWC_SHIFT   (19U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_MASK

#define ADC_STEPCONFIG_SEL_INP_SWC_MASK   (0x00780000U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_1

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_1   (0U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_2

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_2   (1U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_3

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_3   (2U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_4

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_4   (3U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_5

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_5   (4U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_6

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_6   (5U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_7

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_7   (6U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_8

#define ADC_STEPCONFIG_SEL_INP_SWC_CHANNEL_8   (7U)

◆ ADC_STEPCONFIG_SEL_INP_SWC_VREFN

#define ADC_STEPCONFIG_SEL_INP_SWC_VREFN   (8U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_SHIFT

#define ADC_STEPCONFIG_SEL_RFM_SWC_SHIFT   (23U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_MASK

#define ADC_STEPCONFIG_SEL_RFM_SWC_MASK   (0x01800000U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_VSSA

#define ADC_STEPCONFIG_SEL_RFM_SWC_VSSA   (0U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_XNUR

#define ADC_STEPCONFIG_SEL_RFM_SWC_XNUR   (1U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_YNLR

#define ADC_STEPCONFIG_SEL_RFM_SWC_YNLR   (2U)

◆ ADC_STEPCONFIG_SEL_RFM_SWC_VREFN

#define ADC_STEPCONFIG_SEL_RFM_SWC_VREFN   (3U)

◆ ADC_STEPDELAY_RESERVED0_SHIFT

#define ADC_STEPDELAY_RESERVED0_SHIFT   (18U)

◆ ADC_STEPDELAY_RESERVED0_MASK

#define ADC_STEPDELAY_RESERVED0_MASK   (0x00fc0000U)

◆ ADC_STEPDELAY_OPENDELAY_SHIFT

#define ADC_STEPDELAY_OPENDELAY_SHIFT   (0U)

◆ ADC_STEPDELAY_OPENDELAY_MASK

#define ADC_STEPDELAY_OPENDELAY_MASK   (0x0003ffffU)

◆ ADC_STEPDELAY_SAMPLEDELAY_SHIFT

#define ADC_STEPDELAY_SAMPLEDELAY_SHIFT   (24U)

◆ ADC_STEPDELAY_SAMPLEDELAY_MASK

#define ADC_STEPDELAY_SAMPLEDELAY_MASK   (0xff000000U)

◆ ADC_FIFOCOUNT_WORDS_IN_FIFO_SHIFT

#define ADC_FIFOCOUNT_WORDS_IN_FIFO_SHIFT   (0U)

◆ ADC_FIFOCOUNT_WORDS_IN_FIFO_MASK

#define ADC_FIFOCOUNT_WORDS_IN_FIFO_MASK   (0x000001ffU)

◆ ADC_FIFOCOUNT_RESERVED0_SHIFT

#define ADC_FIFOCOUNT_RESERVED0_SHIFT   (7U)

◆ ADC_FIFOCOUNT_RESERVED0_MASK

#define ADC_FIFOCOUNT_RESERVED0_MASK   (0xffffff80U)

◆ ADC_FIFOTHRESHOLD_RESERVED0_SHIFT

#define ADC_FIFOTHRESHOLD_RESERVED0_SHIFT   (6U)

◆ ADC_FIFOTHRESHOLD_RESERVED0_MASK

#define ADC_FIFOTHRESHOLD_RESERVED0_MASK   (0xffffffc0U)

◆ ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_SHIFT

#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_SHIFT   (0U)

◆ ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MASK

#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MASK   (0x000000ffU)

◆ ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MAX

#define ADC_FIFOTHRESHOLD_FIFO_THR_LEVEL_MAX   (256U)

◆ ADC_DMAREQ_DMA_REQUEST_LEVEL_SHIFT

#define ADC_DMAREQ_DMA_REQUEST_LEVEL_SHIFT   (0U)

◆ ADC_DMAREQ_DMA_REQUEST_LEVEL_MASK

#define ADC_DMAREQ_DMA_REQUEST_LEVEL_MASK   (0x0000003fU)

◆ ADC_DMAREQ_RESERVED0_SHIFT

#define ADC_DMAREQ_RESERVED0_SHIFT   (6U)

◆ ADC_DMAREQ_RESERVED0_MASK

#define ADC_DMAREQ_RESERVED0_MASK   (0xffffffc0U)

◆ ADC_FIFODATA_RESERVED1_SHIFT

#define ADC_FIFODATA_RESERVED1_SHIFT   (20U)

◆ ADC_FIFODATA_RESERVED1_MASK

#define ADC_FIFODATA_RESERVED1_MASK   (0xfff00000U)

◆ ADC_FIFODATA_ADCCHNLID_SHIFT

#define ADC_FIFODATA_ADCCHNLID_SHIFT   (16U)

◆ ADC_FIFODATA_ADCCHNLID_MASK

#define ADC_FIFODATA_ADCCHNLID_MASK   (0x000f0000U)

◆ ADC_FIFODATA_ADCDATA_SHIFT

#define ADC_FIFODATA_ADCDATA_SHIFT   (0U)

◆ ADC_FIFODATA_ADCDATA_MASK

#define ADC_FIFODATA_ADCDATA_MASK   (0x00000fffU)

◆ ADC_FIFODATA_RESERVED0_SHIFT

#define ADC_FIFODATA_RESERVED0_SHIFT   (12U)

◆ ADC_FIFODATA_RESERVED0_MASK

#define ADC_FIFODATA_RESERVED0_MASK   (0x0000f000U)

◆ ADC_SYSCONFIG_IDLEMODE_SHIFT

#define ADC_SYSCONFIG_IDLEMODE_SHIFT   (2U)

◆ ADC_SYSCONFIG_IDLEMODE_MASK

#define ADC_SYSCONFIG_IDLEMODE_MASK   (0x0000000cU)

◆ ADC_SYSCONFIG_IDLEMODE_FORCE

#define ADC_SYSCONFIG_IDLEMODE_FORCE   (0U)

◆ ADC_SYSCONFIG_IDLEMODE_NO_IDLE

#define ADC_SYSCONFIG_IDLEMODE_NO_IDLE   (1U)

◆ ADC_SYSCONFIG_IDLEMODE_SMART_IDLE

#define ADC_SYSCONFIG_IDLEMODE_SMART_IDLE   (2U)

◆ ADC_SYSCONFIG_IDLEMODE_SMART_IDLE_WAKEUP

#define ADC_SYSCONFIG_IDLEMODE_SMART_IDLE_WAKEUP   (3U)

◆ ADC_SYSCONFIG_RESERVED1_SHIFT

#define ADC_SYSCONFIG_RESERVED1_SHIFT   (4U)

◆ ADC_SYSCONFIG_RESERVED1_MASK

#define ADC_SYSCONFIG_RESERVED1_MASK   (0xfffffff0U)

◆ ADC_SYSCONFIG_RESERVED0_SHIFT

#define ADC_SYSCONFIG_RESERVED0_SHIFT   (0U)

◆ ADC_SYSCONFIG_RESERVED0_MASK

#define ADC_SYSCONFIG_RESERVED0_MASK   (0x00000003U)