PDK API Guide for J721E
MCAN_MsgRAMConfigParams Struct Reference

Detailed Description

Structure for MCAN Message RAM Configuration Parameters. Message RAM can contain following sections: Standard ID filters, Extended ID filters, TX FIFO(or TX Q), TX Buffers, TX EventFIFO, RX FIFO0, RX FIFO1, RX Buffer. Note: If particular section in the RAM is not used then it's size should be initialized to '0' (Number of buffers in case of Tx/Rx buffer).

Data Fields

uint32_t flssa
 
uint32_t lss
 
uint32_t flesa
 
uint32_t lse
 
uint32_t txStartAddr
 
uint32_t txBufNum
 
uint32_t txFIFOSize
 
uint32_t txBufMode
 
uint32_t txBufElemSize
 
uint32_t txEventFIFOStartAddr
 
uint32_t txEventFIFOSize
 
uint32_t txEventFIFOWaterMark
 
uint32_t rxFIFO0startAddr
 
uint32_t rxFIFO0size
 
uint32_t rxFIFO0waterMark
 
uint32_t rxFIFO0OpMode
 
uint32_t rxFIFO1startAddr
 
uint32_t rxFIFO1size
 
uint32_t rxFIFO1waterMark
 
uint32_t rxFIFO1OpMode
 
uint32_t rxBufStartAddr
 
uint32_t rxBufElemSize
 
uint32_t rxFIFO0ElemSize
 
uint32_t rxFIFO1ElemSize
 

Field Documentation

◆ flssa

uint32_t MCAN_MsgRAMConfigParams::flssa

Standard ID Filter List Start Address

◆ lss

uint32_t MCAN_MsgRAMConfigParams::lss

List Size: Standard ID 0 = No standard Message ID filter 1-127 = Number of standard Message ID filter elements others = Values greater than 128 are interpreted as 128

◆ flesa

uint32_t MCAN_MsgRAMConfigParams::flesa

Extended ID Filter List Start Address

◆ lse

uint32_t MCAN_MsgRAMConfigParams::lse

List Size: Extended ID 0 = No standard Message ID filter 1-64 = Number of standard Message ID filter elements others = Values greater than 64 are interpreted as 64

◆ txStartAddr

uint32_t MCAN_MsgRAMConfigParams::txStartAddr

Tx Buffers Start Address

◆ txBufNum

uint32_t MCAN_MsgRAMConfigParams::txBufNum

Number of Dedicated Transmit Buffers 0 = No Dedicated Tx Buffers 1-32 = Number of Dedicated Tx Buffers others = Values greater than 32 are interpreted as 32

◆ txFIFOSize

uint32_t MCAN_MsgRAMConfigParams::txFIFOSize

Transmit FIFO/Queue Size 0 = No Tx FIFO/Queue 1-32 = Number of Tx Buffers used for Tx FIFO/Queue others = Values greater than 32 are interpreted as 32

◆ txBufMode

uint32_t MCAN_MsgRAMConfigParams::txBufMode

Tx FIFO/Queue Mode 0 = Tx FIFO operation 1 = Tx Queue operation

◆ txBufElemSize

uint32_t MCAN_MsgRAMConfigParams::txBufElemSize

Tx Buffer Element Size

◆ txEventFIFOStartAddr

uint32_t MCAN_MsgRAMConfigParams::txEventFIFOStartAddr

Tx Event FIFO Start Address

◆ txEventFIFOSize

uint32_t MCAN_MsgRAMConfigParams::txEventFIFOSize

Event FIFO Size 0 = Tx Event FIFO disabled 1-32 = Number of Tx Event FIFO elements others = Values greater than 32 are interpreted as 32

◆ txEventFIFOWaterMark

uint32_t MCAN_MsgRAMConfigParams::txEventFIFOWaterMark

Tx Event FIFO Watermark 0 = Watermark interrupt disabled 1-32 = Level for Tx Event FIFO watermark interrupt others = Watermark interrupt disabled

◆ rxFIFO0startAddr

uint32_t MCAN_MsgRAMConfigParams::rxFIFO0startAddr

Rx FIFO0 Start Address

◆ rxFIFO0size

uint32_t MCAN_MsgRAMConfigParams::rxFIFO0size

Rx FIFO0 Size 0 = No Rx FIFO 1-64 = Number of Rx FIFO elements others = Values greater than 64 are interpreted as 64

◆ rxFIFO0waterMark

uint32_t MCAN_MsgRAMConfigParams::rxFIFO0waterMark

Rx FIFO0 Watermark 0 = Watermark interrupt disabled 1-63 = Level for Rx FIFO 0 watermark interrupt others = Watermark interrupt disabled

◆ rxFIFO0OpMode

uint32_t MCAN_MsgRAMConfigParams::rxFIFO0OpMode

Rx FIFO0 Operation Mode 0 = FIFO blocking mode 1 = FIFO overwrite mode

◆ rxFIFO1startAddr

uint32_t MCAN_MsgRAMConfigParams::rxFIFO1startAddr

Rx FIFO1 Start Address

◆ rxFIFO1size

uint32_t MCAN_MsgRAMConfigParams::rxFIFO1size

Rx FIFO1 Size 0 = No Rx FIFO 1-64 = Number of Rx FIFO elements others = Values greater than 64 are interpreted as 64

◆ rxFIFO1waterMark

uint32_t MCAN_MsgRAMConfigParams::rxFIFO1waterMark

Rx FIFO1 Watermark 0 = Watermark interrupt disabled 1-63 = Level for Rx FIFO 1 watermark interrupt others = Watermark interrupt disabled

◆ rxFIFO1OpMode

uint32_t MCAN_MsgRAMConfigParams::rxFIFO1OpMode

Rx FIFO1 Operation Mode 0 = FIFO blocking mode 1 = FIFO overwrite mode

◆ rxBufStartAddr

uint32_t MCAN_MsgRAMConfigParams::rxBufStartAddr

Rx Buffer Start Address

◆ rxBufElemSize

uint32_t MCAN_MsgRAMConfigParams::rxBufElemSize

Rx Buffer Element Size

◆ rxFIFO0ElemSize

uint32_t MCAN_MsgRAMConfigParams::rxFIFO0ElemSize

Rx FIFO0 Element Size

◆ rxFIFO1ElemSize

uint32_t MCAN_MsgRAMConfigParams::rxFIFO1ElemSize

Rx FIFO1 Element Size