Software Diagnostics Library (SDL)

Welcome

This package consists of the Texas Instruments Software Diagnostics Library for J721E family of SoC’s .

The J721E family of SoC’s provides various safety mechanisms and features, as well as recommendations for usage of these safety mechanisms and features. The Software Diagnostic Library (SDL) provides interfaces to these safety mechanisms and features. The provides these interfaces to assist in the development of software applications involving Functional Safety.

In an application involving functional safety, the detection of random hardware faults and ability to take the appropriate response to get the system to a safe state is of utmost importance. Methods to detect and respond to faults in a system are called functional safety mechanisms or safety functions. Examples of safety mechanisms available on an SoC include error correction/detection (ECC) on memory regions, Error Signaling Module (ESM) to monitor error events, etc.

The safety-critical processor product family provides various hardware functional safety mechanisms. For example, this software release provides an API to configure ECC and a reference example to set up interrupts to check on ECC error events detected by hardware. Overall, the system integrator can use this API and implement software diagnostics to meet the safety system goals.

The user of this document should have a general familiarity with the safety-critical processor family.

Table of Contents

• 1. Overview
  • 1.1. Introduction
  • 1.2. Technical Support
  • 1.3. TI Disclaimer
• 2. Release Notes
  • 2.1. Release Notes - 01_01_00
  • 2.2. Release Notes - 01_00_01
  • 2.3. Release Notes - 01_00_00
  • 2.4. Release Notes - 00_02_00
  • 2.5. Release Notes - 00_01_01
  • 2.6. Release Notes - 00_01_00
• 3. Getting Started
  • 3.1. Dependencies
  • 3.2. Building the SDL
  • 3.3. Supported Boards/SOCs
  • 3.4. Loading and Running Examples
• 4. Modules
  • 4.1. ESM : Error Signalling Module
  • 4.2. ECC : Error Correcting Code
  • 4.3. PBIST : Memory Built-In Self-Test
  • 4.4. LBIST : Logic Built-In Self-Test
  • 4.5. VTM : Voltage and Thermal Management
  • 4.6. RTI : RTI/WWDT Windowed Watchdog Timer
  • 4.7. POK: Power OK
  • 4.8. TOG : Time-Out Gasket
  • 4.9. DCC : Dual Clock Comparator
  • 4.10. MCRC : Cyclic Redundancy Check
  • 4.11. R5F CCM: CPU Compare Module
  • 4.12. OSAL
  • 4.13. R5 Core Modules
  • 4.14. ROM_CHECKSUM: ROM Checksum Module
• 5. Safety Examples
  • 5.1. ESM Safety Example
  • 5.2. VTM Safety Example
  • 5.3. POK Safety Example
  • 5.4. TOG Safety Example
  • 5.5. DCC Safety Example
  • 5.6. ECC Safety Example
  • 5.7. RTI Safety Example
  • 5.8. BIST Safety Example
  • 5.9. CPU Safety Example
  • 5.10. MCRC Safety Example
  • 5.11. ROM_Checksum Safety Example
• 6. Diagnostic Mapping
• 7. Developer Notes
  • 7.1. Readback of Written Config and Periodic Readback of Static Config