OSPI Data Structures

Introduction

Macros
#define	CSL_OSPI_POLL_IDLE_TIMEOUT   (5000U) /* in millisecond */
	OSPI operation timeout value. More...
#define	CSL_OSPI_POLL_IDLE_DELAY   (1U) /* in Millisecond */
#define	CSL_OSPI_POLL_IDLE_RETRY   (3U)
#define	CSL_OSPI_REG_RETRY   (10U)
#define	CSL_OSPI_FIFO_WIDTH   (4U)
#define	CSL_OSPI_CMD_LEN_DEFAULT   (1U) /*In bytes */
	OSPI Command default Length. More...
#define	CSL_OSPI_CMD_LEN_EXTENDED   (5U) /*In bytes */
#define	CSL_OSPI_CHIP_SELECT(x)   ((~((1U) << (x))) & 0xFU)
#define	CSL_OSPI_BAUD_RATE_DIVISOR(x)   (((x) - 2U) >> 1U)
	OSPI controller master mode baud rate divisor. SPI bard rate = master_ref_clk/BD, where BD is: 0000 = /2 0001 = /4 0010 = /6 ... 1111 = /32. More...
#define	CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT   (CSL_OSPI_BAUD_RATE_DIVISOR(32U))
#define	CSL_OSPI_DEV_DELAY_ARRAY_SIZE   (4U)
	OSPI device delay parameter array size. More...
#define	CSL_OSPI_DEV_DELAY_CSSOT   (46U) /* Chip Select Start of Transfer Delay */
	OSPI device delays in cycles of SPI master ref clock. More...
#define	CSL_OSPI_DEV_DELAY_CSEOT   (46U) /* Chip Select End of Transfer Delay */
#define	CSL_OSPI_DEV_DELAY_CSDADS   (192U) /* Chip Select De-Assert Different Slaves Delay */
#define	CSL_OSPI_DEV_DELAY_CSDA   (192U) /* Chip Select De-Assert Delay */
#define	CSL_OSPI_SRAM_SIZE_WORDS   (128U)
	SRAM partition configuration definitions. More...
#define	CSL_OSPI_SRAM_PARTITION_RD   (64U)
#define	CSL_OSPI_SRAM_PARTITION_WR
#define	CSL_OSPI_SRAM_PARTITION_DEFAULT   (CSL_OSPI_SRAM_PARTITION_RD - 1U)
#define	CSL_OSPI_SRAM_WARERMARK_RD_LVL   (CSL_OSPI_SRAM_PARTITION_RD / 4U)
	SRAM fill level watermark. More...
#define	CSL_OSPI_SRAM_WATERMARK_WR_LVL   (CSL_OSPI_SRAM_PARTITION_WR / 4U)
#define	CSL_OSPI_INTR_MASK_IND_XFER
#define	CSL_OSPI_INTR_MASK_ALL
#define	CSL_OSPI_CMD_READ_SINGLE_DUMMY_CLOCKS   (0U)
	Number of dummy cycles for a command read. More...
#define	CSL_OSPI_CMD_READ_OCTAL_DUMMY_CLOCKS   (8U)
#define	CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_MODE   (0U)
	PHY Master control register master/bypass mode field value. More...
#define	CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_BYPASS_MODE   (1U)

Macro Definition Documentation

CSL_OSPI_POLL_IDLE_TIMEOUT

#define CSL_OSPI_POLL_IDLE_TIMEOUT   (5000U) /* in millisecond */

OSPI operation timeout value.

CSL_OSPI_POLL_IDLE_DELAY

#define CSL_OSPI_POLL_IDLE_DELAY   (1U) /* in Millisecond */

CSL_OSPI_POLL_IDLE_RETRY

#define CSL_OSPI_POLL_IDLE_RETRY   (3U)

CSL_OSPI_REG_RETRY

#define CSL_OSPI_REG_RETRY   (10U)

CSL_OSPI_FIFO_WIDTH

#define CSL_OSPI_FIFO_WIDTH   (4U)

CSL_OSPI_CMD_LEN_DEFAULT

#define CSL_OSPI_CMD_LEN_DEFAULT   (1U) /*In bytes */

OSPI Command default Length.

CSL_OSPI_CMD_LEN_EXTENDED

#define CSL_OSPI_CMD_LEN_EXTENDED   (5U) /*In bytes */

CSL_OSPI_CHIP_SELECT

#define CSL_OSPI_CHIP_SELECT

(

x

)

((~((1U) << (x))) & 0xFU)

CSL_OSPI_BAUD_RATE_DIVISOR

#define CSL_OSPI_BAUD_RATE_DIVISOR

(

x

)

(((x) - 2U) >> 1U)

OSPI controller master mode baud rate divisor. SPI bard rate = master_ref_clk/BD, where BD is: 0000 = /2 0001 = /4 0010 = /6 ... 1111 = /32.

CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT

#define CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT   (CSL_OSPI_BAUD_RATE_DIVISOR(32U))

CSL_OSPI_DEV_DELAY_ARRAY_SIZE

#define CSL_OSPI_DEV_DELAY_ARRAY_SIZE   (4U)

OSPI device delay parameter array size.

CSL_OSPI_DEV_DELAY_CSSOT

#define CSL_OSPI_DEV_DELAY_CSSOT   (46U) /* Chip Select Start of Transfer Delay */

OSPI device delays in cycles of SPI master ref clock.

CSL_OSPI_DEV_DELAY_CSEOT

#define CSL_OSPI_DEV_DELAY_CSEOT   (46U) /* Chip Select End of Transfer Delay */

CSL_OSPI_DEV_DELAY_CSDADS

#define CSL_OSPI_DEV_DELAY_CSDADS   (192U) /* Chip Select De-Assert Different Slaves Delay */

CSL_OSPI_DEV_DELAY_CSDA

#define CSL_OSPI_DEV_DELAY_CSDA   (192U) /* Chip Select De-Assert Delay */

CSL_OSPI_SRAM_SIZE_WORDS

#define CSL_OSPI_SRAM_SIZE_WORDS   (128U)

SRAM partition configuration definitions.

size of the indirect read/write partition in the SRAM, in units of SRAM locations

CSL_OSPI_SRAM_PARTITION_RD

#define CSL_OSPI_SRAM_PARTITION_RD   (64U)

CSL_OSPI_SRAM_PARTITION_WR

#define CSL_OSPI_SRAM_PARTITION_WR

Value:

(CSL_OSPI_SRAM_SIZE_WORDS - \
                                         CSL_OSPI_SRAM_PARTITION_RD)

CSL_OSPI_SRAM_PARTITION_DEFAULT

#define CSL_OSPI_SRAM_PARTITION_DEFAULT   (CSL_OSPI_SRAM_PARTITION_RD - 1U)

CSL_OSPI_SRAM_WARERMARK_RD_LVL

#define CSL_OSPI_SRAM_WARERMARK_RD_LVL   (CSL_OSPI_SRAM_PARTITION_RD / 4U)

SRAM fill level watermark.

CSL_OSPI_SRAM_WATERMARK_WR_LVL

#define CSL_OSPI_SRAM_WATERMARK_WR_LVL   (CSL_OSPI_SRAM_PARTITION_WR / 4U)

CSL_OSPI_INTR_MASK_IND_XFER

#define CSL_OSPI_INTR_MASK_IND_XFER

Value:

(CSL_OSPI_INTR_MASK_IND_OP_DONE         | \
                                     CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH | \
                                     CSL_OSPI_INTR_MASK_IND_RD_SRAM_FULL)

CSL_OSPI_INTR_MASK_ALL

#define CSL_OSPI_INTR_MASK_ALL

Value:

(CSL_OSPI_INTR_MASK_MODE_M_FAIL         | \
                                 CSL_OSPI_INTR_MASK_UNDERFLOW_DET       | \
                                 CSL_OSPI_INTR_MASK_IND_OP_DONE         | \
                                 CSL_OSPI_INTR_MASK_IND_RD_REJECT       | \
                                 CSL_OSPI_INTR_MASK_PROT_WR_ATTEMPT     | \
                                 CSL_OSPI_INTR_MASK_ILLEGAL_ACCESS_DET  | \
                                 CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH | \
                                 CSL_OSPI_INTR_MASK_IND_RD_SRAM_FULL    | \
                                 CSL_OSPI_INTR_MASK_POLL_EXP_INT)

CSL_OSPI_CMD_READ_SINGLE_DUMMY_CLOCKS

#define CSL_OSPI_CMD_READ_SINGLE_DUMMY_CLOCKS   (0U)

Number of dummy cycles for a command read.

CSL_OSPI_CMD_READ_OCTAL_DUMMY_CLOCKS

#define CSL_OSPI_CMD_READ_OCTAL_DUMMY_CLOCKS   (8U)

CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_MODE

#define CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_MODE   (0U)

PHY Master control register master/bypass mode field value.

CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_BYPASS_MODE

#define CSL_OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_BYPASS_MODE   (1U)